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參數(shù)資料
| 型號(hào)： | M2201 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2-Wires 1 Kbit x8 Serial EEPROM |
| 中文描述： | 2 - 1千位x8線串行EEPROM |
| 文件頁(yè)數(shù)： | 3/15頁(yè) |
| 文件大?。?/td> | 111K |
| 代理商： | M2201 |
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AI01100
VCC
CBUS
SDA
RL
MASTER
RL
SCL
CBUS
100
200
300
400
0
4
8
12
16
20
CBUS (pF)
R
)
VCC = 5V
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
)
SIGNAL DESCRIPTIONS
Serial Clock (SCL).
The SCL input pin is used to
synchronize all data in and out of the memory. A
resistor can be connected from the SCL line to V
CC
to act as a pull up (see Figure 3).
Serial Data (SDA).
The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. A resistor must be connected from the SDA
bus line to V
CC
to act as pull up (see Figure 3).
Write Control (WC).
An hardware Write Control
feature (WC) is offered on pin 7. This feature is
usefull to protect the contents of the memory from
any erroneous erase/write cycle. The Write Control
signal is used to enable (WC = V
IH
) or disable (WC
= V
IL
) the internal write protection. When uncon-
nected, the WC input is internally read as V
IL
(WC
is disabled).
DEVICE OPERATION
The device that controls the data transfer is known
as the master. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The M2201 is always a slave device
in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the M2201 continu-
ously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition.
STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the M2201 and the
bus master. A STOP condition at the end of a Read
command forces the standby state. A STOP condi-
tion at the end of a Write command triggers the
internal EEPROM write cycle.
Acknowledge Bit (ACK).
An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input.
During data input the M2201 sample
the SDA bus signal on the rising edge of the clock
SCL. Note that for correct device operation the SDA
signal must be stable during the clock low to high
transition and the data must change ONLY when
the SCL line is low.
3/15
M2201
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| M220123BLJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, Clock Oscillator |
| M220123BMJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, Clock Oscillator |
| M220123BP.L.MJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, LVPECL/LVDS/CML, Clock Oscillator |
| M220123BPJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, Clock Oscillator |
| M220123GLJ | 制造商:MTRONPTI 制造商全稱:MTRONPTI 功能描述:9x14 mm, 3.3/2.5/1.8 Volt, PECL/LVDS/CML, Clock Oscillator |
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