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參數(shù)資料
| 型號(hào)： | M2052-12-622.0800 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | VOLTAGE CONTROLLED CLOCK SAW OSCILLATOR, 622.08 MHz |
| 封裝： | LEADLESS, CERAMIC PACKAGE-36 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 504K |
| 代理商： | M2052-12-622.0800 |
M2050/51/52 Datasheet Rev 1.0
6 of 12
Revised 23Jun2005
Integrate d Circu it Systems, Inc. ● Communications Modules ● www.ics t.com ● tel (508) 852-5400
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminar y In f o r m atio n
forced to its upper or lower operating limit which is
typically about 250 ppm above or below the VCSO
center frequency (no more than 500 ppm above or
below).
In normal phase-locked condition, the instantaneous
phase error is measured by the phase detector and is
converted to charge pump current pulses. These
current pulses are then integrated by the external loop
filter to create a VCSO control voltage. The loop filter
acts as a low pass filter to remove unwanted reference
clock jitter above a determined frequency or PLL
bandwidth. For reference phase jitter frequencies within
the loop bandwidth, phase jitter amplitude is passed on
to the output clock according to the PLL loop frequency
response curve.
The relationship between the nominal VCSO center
frequency (Fvcso), the Mfin divider, the Mfec divider,
the Rfec divider, and the input reference frequency (Fin)
is:
The Mfec, Rfec, and Mfin dividers can be set by pin
configuration using the input pins FEC_SEL1, FEC_SEL0,
FIN_SEL1, and FIN_SEL0
.
Post-PLL Divider
The M2050/51/52 also features a post-PLL (P) divider.
Through use of the P divider, the device’s output
frequency (Fout) can be that of the VCSO (such as
625.00MHz
) or the VCSO frequency divided by 4, 5 or
25
.
The P_SEL2:0 pins select the value for the P divider.
Accounting for the P divider, the complete relationship
between the input clock reference frequency (Fin) and
output clock frequency (Fout) is defined as:
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
TriState
The TriState feature puts the LVPECL output driver into
a high impedance state, effectively disconnecting the
driver from the FOUT and nFOUT pins of the device. A
logic 0 is then present on the clock net. The impedance
of the clock net is then set to 50
by the external circuit
resistors. (This is in distinction to a CMOS output in
TriState, in which case the net goes to a high
impedance and the logic value floats.) The 50
impedance level of the LVPECL TriState allows
manufacturing In-circuit Test to drive the clock net with
an external 50
generator to validate the integrity of
clock net and the clock load.
Any unused output (single-ended or differential) should
be left unconnected (floating) in system application.
This minimizes output switching current and therefore
minimizes noise modulation of the VCSO.
Narrow Bandwidth (NBW) Control Pin
A Narrow Loop Bandwidth control pin (NBW pin) is
included to enable adjustment of the PLL loop
bandwidth. In wide bandwidth mode (NBW=0), the
internal resistor Rin is 100k
. With the NBW pin
asserted (NBW=1), the internal resistor Rin is changed to
2100k
. This lowers the loop bandwidth by a factor of
about 21 (approximately 2100 / 100) and lowers the
damping factor by a factor of about 4.6 (the square root
of 21), assuming the same external loop filter
component values.
Loss of Lock Indicator (LOL) Output Pin
Under normal device operation, when the PLL is
locked, the LOL Phase Detector drives LOL to logic 0.
Under circumstances when the VCSO cannot fully
phase lock to the input (as measured by a greater than
4 ns discrepancy between the feedback and reference
clock rising edges at the LOL Phase Detector) the LOL
output goes to logic 1. The LOL pin will return back to
logic 0 when the phase detector error is less than 2 ns.
The loss of lock indicator is a low current LVCMOS
output.
Guidelines for Using LOL
In a given application, the magnitude of peak-to-peak
jitter at the phase detector will usually increase as the
Rfec divider is increased. If the LOL pin will be used to
detect an unusual clock condition, or a clock fault, the
FEC_SEL1:0
pins should be set to provide a phase
detector frequency of 5MHz or greater (the phase
detector frequency is equal to Fin divided by the Rfec
divider). Otherwise, false LOL indications may result. A
phase detector frequency of 10MHz or greater is
desirable when reference jitter is over 500ps, or when
the device is used within a noisy system environment.
LOL
should not be used when the device is used in a
loop timing application.
Fvcso
Fin
Mfin
×
Mfec
Rfec
--------------
×
=
Fout
Fvcso
P
-------------------
=
Fin
Mfin Mfec
×
Rfec P
×
---------------------------------
×
=
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