參數(shù)資料
型號： M2051-13I669.3266
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： XO, clock
英文描述： VOLTAGE CONTROLLED CLOCK SAW OSCILLATOR, 669.3266 MHz
封裝： LEADLESS, CERAMIC PACKAGE-36
文件頁數(shù)： 5/12頁
文件大?。?/td> 504K
代理商： M2051-13I669.3266
M2050/51/52 Datasheet Rev 1.0
2 of 12
Revised 23Jun2005
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Preliminar y In f o r m atio n
PIN DESCRIPTIONS
Number
Name
I/O
Configuration
Description
1, 2, 3, 10, 14, 26
GND
Ground
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12
13
FOUT1
nFOUT1
Output
No internal terminator
Clock output pair 1. Differential LVPECL.
15
16
FOUT0
nFOUT0
Output
No internal terminator
Clock output pair 0. Differential LVPECL.
17
18
25
P_SEL1
P_SEL0
P_SEL2
Input
Internal pull-down resistor1
Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 10.
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 7,
20
nDIF_REF1
Input
Biased to Vcc/2 2
Note 2: Biased toVcc/2, with 50k
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
21
DIF_REF1
Internal pull-down resistor1
22
REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL:
Logic 1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
23
nDIF_REF0
Input
Biased to Vcc/2 2
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
24
DIF_REF0
Internal pull-down resistor 1
27
28
FIN_SEL1
FIN_SEL0
Input
Internal pull-down resistor1
I
nput clock frequency selection. LVCMOS/LVTTL. See
29
30
FEC_SEL0
FEC_SEL1
Input
Internal pull-down resistor1
Mfec and Rfec divider value selection. LVCMOS/ LVTTL.
See Tables 4, 5,and 6 on pg. 3.
31
LOL
Output
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase. 3
Logic 1 indicates loss of lock.
Logic 0 indicates locked condition.
32
NBW
Input
Internal pull-UP resistor1
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic 1 - Narrow loop bandwidth, R
IN = 2100k.
Logic 0 - Wide bandwidth, R
IN = 100k.
34, 35, 36
DNC
Do Not Connect.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M2052 制造商:ICS 制造商全稱:ICS 功能描述:SAW PLL FOR 10GBE 64B/66B FEC
M2052-11-625.0000 制造商:ICS 制造商全稱:ICS 功能描述:SAW PLL FOR 10GBE 64B/66B FEC
M2052-11I625.0000 制造商:ICS 制造商全稱:ICS 功能描述:SAW PLL FOR 10GBE 64B/66B FEC
M2053-11-644.5313 功能描述:時鐘合成器/抖動清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
M2053-11-644.5313T 功能描述:時鐘合成器/抖動清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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