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參數(shù)資料
| 型號： | M2050-11-669.3120 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | VOLTAGE CONTROLLED CLOCK SAW OSCILLATOR, 669.312 MHz |
| 封裝： | LEADLESS, CERAMIC PACKAGE-36 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 504K |
| 代理商： | M2050-11-669.3120 |
M2050/51/52 Datasheet Rev 1.0
Revised 23Jun2005
Integ r ated Circu it Systems, Inc. ● Communicatio ns Module s ● www.ics t.com ● te l (508) 852-5400
M2050/51/52
SAW PLL FOR 10GBE 64B/66B FEC
Prelimina r y Inf o r m ation
GENERAL DESCRIPTION
The M2050/51/52 is a VCSO (Voltage Controlled SAW
Oscillator) based clock PLL
designed for FEC clock ratio
translation in 10Gb optical systems
such as 10GbE 64b/66b. It supports
both mapping and de-mapping of
64b/66b encoding and FEC
(Forward Error Correction) clock
multiplication ratios. The ratios are pin-selected from
pre-programming look-up tables.
FEATURES
◆ Integrated SAW delay line; Output of 15 to 700 MHz *
◆ Low phase jitter < 0.5 ps rms typical
(12kHz to 20MHz or 50Hz to 80MHz)
◆ Pin-selectable PLL divider ratios support 64b/66b and
FEC encoding/decoding ratios:
M2050: Map 10GbE to LAN, 255/238 FEC, or 255/237 FEC
M2051: De-map 10GbE LAN or 255/238 FEC to 10GbE
M2052: De-map 255/237 FEC & 255/238 FEC to 10GbE LAN
◆ Scalable dividers provide further adjustment of loop
bandwidth as well as jitter tolerance
◆ LVPECL clock output (CML and LVDS options available)
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Loss of Lock (LOL) output pin
◆ Narrow Bandwidth control input (NBW Pin)
◆ Hitless Switching (HS) options with or without Phase
Build-out (PBO) available; performance conforms with
SONET (GR-253) /SDH (G.813) MTIE and TDEV during
reference clock reselection
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
* Specify VCSO center frequency at time of order.
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example I/O Clock Frequency Combinations
Using M2050 Mapper PLL
Base Input
Rate (MHz)1
Note 1: Input reference clock can be base rate divided by “Mfin”.
Mapper Ratio
Mfec / Rfec
(Pin Selectable)
VCSO* and Base
Output Rate
(MHz)2
Note 2: Output rate can be base rate divided by “P”.
625.0000
33 / 32
644.5313
625.0000
15 / 14
669.6429
644.5313
15 / 14
690.5692
FEC_SEL1:0
FIN_SEL1:0
P_SEL2:0
Loop
M2050/51/52 SAW PLL for 10GbE 64b/66b FEC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M2050-11I625.0000 | VOLTAGE CONTROLLED CLOCK SAW OSCILLATOR, 625 MHz |
| M2050-12I690.5692 | VOLTAGE CONTROLLED CLOCK SAW OSCILLATOR, 690.5692 MHz |
| M2051-12-690.5692 | VOLTAGE CONTROLLED CLOCK SAW OSCILLATOR, 690.5692 MHz |
| M2051-12IFREQ | VOLTAGE CONTROLLED CLOCK SAW OSCILLATOR, 15 MHz - 700 MHz |
| M2052-11-625.0000 | VOLTAGE CONTROLLED CLOCK SAW OSCILLATOR, 625 MHz |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2050-11-693.4830 | 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk |
| M2050-11-693.4830T | 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Tape and Reel |
| M2050-11I644.5313 | 制造商:ICS 制造商全稱:ICS 功能描述:SAW PLL FOR 10GBE 64B/66B FEC |
| M2050-11I693.4830 | 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk |
| M2050-11I693.4830T | 制造商:Integrated Device Technology Inc 功能描述:FREQUENCY TRANSLATOR 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Tape and Reel |
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