- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄26738 > M2006-12-670.8386LF (INTEGRATED DEVICE TECHNOLOGY INC) PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 PDF資料下載
參數(shù)資料
| 型號： | M2006-12-670.8386LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 374K |
| 代理商： | M2006-12-670.8386LF |
M2006-12 Datasheet Rev 1.0
7 of 8
Revised 13Jul2004
Integr ated Circuit Systems , Inc. ● Netw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (5 08) 85 2-54 00
M2006-12
VCSO BASED FEC CLOCK PLL
Prod uct Data Sh eet
ELECTRICAL SPECIFICATIONS (CONTINUED)
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Figure 5: Output Rise and Fall Time
Output Duty Cycle
Figure 6: Output Duty Cycle
AC Characteristics
Unless stated otherwise, V
CC = 3.3V +5%,TA = 0
oC to +70 oC (commercial), T
A = -40
oC to +85 oC (industrial), F
VCSO = FOUT = 622-675MHz,
LVPECL outputs terminated with 50
to V
CC - 2V
Symbol Parameter
Min
Typ
Max
Unit Test Conditions
Input
Frequency
Range
F
IN
Input Frequency
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
10
700
MHz
Output
Frequency
F
FOUT
Output Frequency
Range
FOUT0, nFOUT0,
FOUT1, nFOUT1
100
700
MHz
APR
VCSO Pull-Range
Commercial
±120
±200
ppm
Industrial
±50
±150
ppm
PLL Loop
Constants 1
Note 1: Parameters needed for PLL Simulator software; see PLL Simulator Tool Available on pg. 5.
K
VCO
VCO Gain
800
kHz/V
R
IN
Internal Loop Resistor
50
k
BW
VCSO
VCSO Bandwidth
700
kHz
Phase Noise
and Jitter
Φn
Single Side Band
Phase Noise
@622.08MHz
1
kHz Offset
-72
dBc/Hz
Fin=19.44 MHz
Mfin=32, Mfec=1, Rfec=1
10
kHz Offset
-94
dBc/Hz
100
kHz Offset
-123
dBc/Hz
J(t)
Jitter (rms)
@622.08MHz
12kHz to 20MHz
0.5
ps rms
50kHz to 80MHz
0.5
ps rms
t
PW
Output Duty Cycle 2
FOUT0, nFOUT0,
FOUT1, nFOUT1
Note 2: See Parameter Measurement Information on pg. 7.
P0, P1 = 1
40
50
60
%
P0, P1 = 4
45
50
55
%
t
R
Output Rise Time 2
FOUT0, nFOUT0,
FOUT1, nFOUT1
200
450
500
ps
20
% to 80%
t
F
Output Fall Time 2
200
450
500
ps
20
% to 80%
Table 10: AC Characteristics
20%
80%
tR
20%
tF
80%
Clock Output
V
P
-P
nFOUT
FOUT
t
PW
t
PERIOD
(Output Pulse Width)
tPERIOD
tPW
odc =
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M2006-12I-622.0800 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-12I-672.1600 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-12-644.5313 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-12I-690.5692 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M210E622.08-147M | SPECIALTY LOGIC CIRCUIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2006-12A | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
| M2006-12A-622.0800 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
| M2006-12A-625.0000 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
| M2006-12A-669.3266 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
| M2006-12A-669.6429 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。