- 您現在的位置：買賣IC網 > PDF目錄26738 > M2006-02A-669.1281LF (INTEGRATED DEVICE TECHNOLOGY INC) PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 PDF資料下載
參數資料
| 型號： | M2006-02A-669.1281LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數： | 5/8頁 |
| 文件大?。?/td> | 408K |
| 代理商： | M2006-02A-669.1281LF |
M2006-02A Datasheet Rev 1.0
5 of 8
Revised 28Jul2004
Integr ated Circuit Systems , Inc. ● Ne tw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (508 ) 85 2-54 00
M2006-02A
VCSO BASED FEC CLOCK PLL
Prod uct Data Sh eet
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M2006-02A requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 4).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
Figure 4: External Loop Filter
PLL bandwidth is affected by loop filter component
values, “Mfec” and “Mfin” values, and the “PLL Loop
The various “Non-FEC ratio” settings can be used to
actively change PLL loop bandwidth in a given
application. See “FEC PLL Ratio Dividers Look-up
PLL Simulator Tool Available
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
Example External Loop Filter Component Values1
VCSO Parameters: KVCO = 800kHz/V, RIN = 50k, VCSO Bandwidth = 700kHz.
Device Configuration
Example External Loop Filter Component Values
Nominal Performance Using These Values
FRef
(MHz)
F
VCSO (MHz) FIN_SEL1:0
pins
FEC_ SEL3:0
pins
R loop
C loop
R post
C post
PLL Loop
Bandwidth
Damping
Factor
Passband
Peaking (dB)
19.44
622.08
0 0
1 1 0 0
11.5
k
2.2
F
34
k
470
pF
1k
Hz
6.0
0.05
77.76
0 1
1 1 1 0
155.52
1 0
1 1 1 1
622.08
1 1
0 1 1 0
5.11
k
4.7
F
6.0
0.06
167.3317
1 0
0 0 0 1
113.0
k
0.22
F
6.0
0.06
669.3266
1 1
28.0
k
1.0
F
6.3
0.05
155.52
669.3266
1 0
1 0 0 1
121.0
k
0.22
F
6.0
0.05
622.08
1 1
30.1
k
1.0
F
6.5
0.05
Note 1: K
VCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor, and
Passband Peaking. For PLL Simulator software, go to www.icst.com.
ABSOLUTE MAXIMUM RATINGS1
Symbol Parameter
Rating
Unit
V
I
Inputs
-0.5 to V
CC +0.5
V
O
Outputs
-0.5 to V
CC +0.5
V
CC
Power Supply Voltage
4.6
V
T
S
Storage Temperature
-45 to +100
oC
Table 9: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
相關PDF資料 |
PDF描述 |
|---|---|
| M2006-02AI669.6429 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-04-622.0800LF | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-12-669.1281 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-12I-669.6429 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-12-644.5313LF | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M2006-02A-693.4830 | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk |
| M2006-02A-693.483T | 功能描述:時鐘合成器/抖動清除器 FREQUENCY TRANSLATOR RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| M2006-02AI622.0800 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL |
| M2006-02AI625.0000 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL |
| M2006-02AI669.3266 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL |
發(fā)布緊急采購，3分鐘左右您將得到回復。