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參數(shù)資料
| 型號(hào)： | M2006-02A-644.5313 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 408K |
| 代理商： | M2006-02A-644.5313 |
M2006-02A Datasheet Rev 1.0
Revised 28Jul2004
Integr ated Circuit Systems , Inc. ● Ne tw o r ki ng & C o mmun ica t io ns ● ww w. icst.com ● tel (508 ) 85 2-5 400
M2006-02A
VCSO BASED FEC CLOCK PLL
Product Data Sheet
GENERAL DESCRIPTION
The M2006-02A is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PLL designed for clock frequency
translation and jitter attenuation.
The device supports both forward
and inverse FEC (Forward Error
Correction) clock multiplication
ratios. Multiplication ratios are
pin-selected from pre-programming look-up tables.
FEATURES
◆ Reduced intrinsic output jitter and improved power
supply noise rejection compared to M2006-02
◆ Low phase jitter of 0.25 ps rms typical
(12kHz to 20MHz or 50kHz to 80MHz)
◆ Pin-selectable PLL divider ratios support forward and
inverse FEC ratio translation, including:
255/238 (OTU1) Mapping and 238/255 De-mapping
255/237 (OTU2) Mapping and 237/255 De-mapping
255/236 (OTU3) Mapping and 236/255 De-mapping
◆ Input reference and VCSO frequencies up to 700MHz,
supports loop timing modes
(Specify VCSO frequency at time of order)
◆ Supports active switching between inverse-FEC and
non-FEC clock ratios (same VCSO center frequency)
◆ Ideal for complex ratio FEC ratio translation and
for use with an unstable reference (i.e., similar to the
M2006-12A - and pin-compatible - but without the
Hitless Switching and Phase Build-out functions)
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
Example I/O Clock Combinations
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Using M2006-02A-622.0800
PLL Ratio
Input Clock (MHz)
Output Clock (MHz)
1/1
622.08, 155.52,
77.76, or 19.44
622.08
or
155.52
237/255
(inverse FEC)
669.3266, 167.3316,
83.6658, or 20.9165
Using M2006-02A-669.3266
PLL Ratio
Input Clock (MHz)
Output Clock (MHz)
237/255
(FEC rate)
622.08, 155.52,
77.76, or 19.44
669.3266
or
167.3316
1/1
669.3266, 167.3316,
83.6658, or 20.9165
P0_SEL
P1_SEL
M2006-02
Loop
Filter
A
M2006-02A VCSO Based FEC Clock PLL
相關(guān)PDF資料 |
PDF描述 |
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| M2006-02A-669.1281LF | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2006-02AI669.6429 | PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M2006-02A-666.5143 | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk |
| M2006-02A-666.514T | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Tape and Reel |
| M2006-02A-669.3266 | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Bulk |
| M2006-02A-669.326T | 制造商:Integrated Device Technology Inc 功能描述:9X9 LCC(LEAD FREE) - Tape and Reel |
| M2006-02A-669.6429 | 制造商:ICS 制造商全稱:ICS 功能描述:VCSO BASED FEC CLOCK PLL |
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