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參數(shù)資料
| 型號(hào)： | M2004-51-622.0800 |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大小： | 459K |
| 代理商： | M2004-51-622.0800 |
M2004-x1 Datasheet Rev 1.1
2 of 12
Revised 16Jul2003
Integr ate d Circuit Systems , In c. ● Comm unication s Modules ● www.icst.com ● tel (508) 852-5400
M2004-X1
FREQUENCY TRANSLATION PLL SERIES
Preliminar y In f o r m atio n
PIN DESCRIPTIONS
Number
Name
I/O
Configuration
Description
1, 2, 3, 10, 14, 26
GND
Ground
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections. See Figure 5,
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33
VCC
Power
Power supply connection, connect to +3.3V.
12
13
N0
N1
Input
Internal pull-down resistor1
Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 8.
N divider (output divider) inputs N1:0.
LVCMOS/LVTTL. See Table 6, Pin Selection of N
15
16
FOUT
nFOUT
Output
No internal terminator
Clock output pair. Differential LVPECL.
17
MR
Input
Internal pull-down resistor1
Reset:
Logic 1 resets M and N dividers and forces
FOUT
to LOW and nFOUT to HIGH.
Logic 0 enables the outputs.
LVCMOS/LVTTL. See Table 9, Pin Configuration &
18
20
21
S_CLOCK
S_DATA
S_LOAD
Input
Internal pull-down resistors1
Serial programming input pins. LVCMOS/LVTTL.
See Table 9, Pin Configuration & Serial
Programming Functions, on pg. 5 for how these
three pins are used in combination.
22
nP_LOAD
Input
Internal pull-down resistor1
Pin-configuration vs. serial programming control.
Determines when data present at M5:0 and N1:0 is
loaded into M and N dividers vs. when serial
programming occurs. LVCMOS/LVTTL. See
Functions, on pg. 5 for how this pin is used.
23
REF_CLK1
Input
Internal pull-down resistor1
Reference clock inputs. LVCMOS/LVTTL.
24
REF_CLK0
Internal pull-down resistor1
25
REF_SEL
Input
Internal pull-down resistor1
Reference clock input selection. LVCMOS/LVTTL.
See Table 4, Reference Clock Input Selection, on
pg. 3. REF_SEL triggers Hitless Switching (HS/PBO)
when toggled.
27
28
29
30
31
M0
M1
M2
M3
M4
Input
Internal pull-down resistor1
M divider (feedback divider) inputs M5:0. See
32
M5
Internal pull-up resistor1
34, 35, 36
DNC
Do Not Connect.
Table 3: Pin Descriptions
相關(guān)PDF資料 |
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| M2004-21-622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-31I622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-21I622.0800 | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-31-622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-51I622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
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