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參數(shù)資料
| 型號： | M2004-32-622.0800 |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2004 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大?。?/td> | 403K |
| 代理商： | M2004-32-622.0800 |
M2004-x2 Datasheet Rev 1.3
3 of 10
Revised 10Sep2003
M2004-X2
FREQUENCY TRANSLATION PLL FAMILY
Preliminar y In f o r m atio n
DETAILED BLOCK DIAGRAM
Figure 3: Detailed Block Diagram
PLL DIVIDER SELECTION TABLES
Reference Clock Input Selection
M Divider Pin Selection
N Divider Pin Selection
M2004-x2
VC
nVC
nOP_OUT
OP_OUT
OP_IN
nOP_IN
M Divider
M = 3-63
Pin Configuration Register
6
M5:0
N1:0
Phase
Detector
nFOUT
MR
2
REF_SEL
Pin Setting
(Pin 22)
Reference Input Selection
0
DIF_REF, nDIF_REF
1
REF_CLK
Table 4: Reference Clock Input Selection
M5:0
Pin
Settings
(Pins 32 - 27)
M5
-
M0
Definition
Sample Input Clock
Freq (MHz)
F
VCSO=
F
VCSO=
622.08
1, 625.002
Note 1: F
VCSO = 622.08 MHz (e.g., M2004-22-622.0800)
Note 2: F
VCSO = 625.00 MHz (e.g., M2004-22-625.0000)
53 4 3 2 1 0
Note 3: M5 pin has a pull-up resister; M4-M0, pull-down.
Feedback Divider Value “M”
0 0 0 0 1 1
M = 3
minimum
0 0 0 1 0 0
M = 4
155.52
156.25
0 0 1 0 0 0
M = 8
77.76
0 1 0 0 0 0
M = 16
38.80
0 1 1 0 0 1
M = 25
25.00
1 0 0 0 0 0
M = 32
19.44
1 1 1 1 1 1
M = 63
Table 5: M Divider Pin Selection
N1:0 Settings
(Pin 13 and 12)
N1
N0
N Divider
Value
Sample Output
Frequency (MHz) 1
(FOUT, nFOUT)
Note 1: F
VCSO = 622.08MHz (e.g., M2004-22-622.0800)
0
1
622.08
0
1
2
311.04
1
0
4
155.52
1
8
77.76
Table 6: N Divider Pin Selection
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| M2004-42I622.0800LF | 2004 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
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