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| 型號： | M2004-31I622.0800LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 459K |
| 代理商： | M2004-31I622.0800LF |
M2004-x1 Datasheet Rev 1.1
3 of 12
Revised 16Jul2003
M2004-X1
FREQUENCY TRANSLATION PLL SERIES
Preliminar y In f o r m atio n
DETAILED BLOCK DIAGRAM
Figure 3: Detailed Block Diagram
DEVICE CONFIGURATION TABLES
Reference Clock Input Selection
M and N Pin Selection Option
M and N Pin Selection Option (Continued)
Serial Programming Alternative (Using S_DATA Pin)
M2004-x1
VC
nVC
nOP_OUT
OP_OUT
OP_IN
nOP_IN
M Divider
M = 3-511
6
M5:0
N1:0
Phase
Detector
nFOUT
MR
2
M8:0
REF_SEL
Pin Setting
(Pin 25)
Reference Input Selection
0
REF_CLK0
1
REF_CLK1
Pin Selection of M Divider Using M5:0 Pins
M5:0
Pin
Settings1
(Pins 32 - 27)
M5
-
M0
Note 1: Bits M8:6 default to 0.
Definition
Sample Input Clock
Freq (MHz)
F
VCSO=
F
VCSO=
622.08
2, 625.003
Note 2: F
VCSO = 622.08 MHz (e.g., M2004-21-622.0800)
Note 3: F
VCSO = 625.00 MHz (e.g., M2004-21-625.0000)
54 4 3 2 1 0
Note 4: M5 pin has a pull-up resister; M4-M0, pull-down.
Feedback Divider Value “M”
0 0 0 0 1 1
M = 3
minimum
0 0 0 1 0 0
M = 4
155.52
156.25
0 0 1 0 0 0
M = 8
77.76
0 1 0 0 0 0
M = 16
38.80
0 1 1 0 0 1
M = 25
25.00
1 0 0 0 0 0
M = 32
19.44
1 1 1 1 1 1
M = 63
Pin Selection of N Divider Using N1:0 Pins
N1
:0 Settings
(Pin 13 and 12)
N1
N0
N Divider
Value
Sample Output
Frequency (MHz) 1
(FOUT, nFOUT)
Note 1: F
VCSO = 622.08MHz (e.g., M2004-21-622.0800)
0
1
622.08
0
1
2
311.04
1
0
4
155.52
1
8
77.76
Serial
Bits
Settings per
Bit
Definition
T1:0
1 0
Normal/Test Mode
0 0
Normal Operation
*
*Note: T1 and T0, used for test automation, must be set to 0
N1:0
1 0
Output Divider Value “N”
0 0
N = 1
minimum
1 1
N = 8
maximum
M8:0 8 7 6 5 4 3 2 1 0
Feedback Divider Value “M”
0 0 0 0 0 0 0 1 1
M = 3
minimum
0 0 0 1 0 0 0 0 0
M = 32
0 0 0 1 1 1 1 1 1
M = 63
1 1 1 1 1 1 1 1 1
M = 511
maximum
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| M2004-21I622.0800 | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-31-622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-51I622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-42-622.0800LF | 2004 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| M2004-32-622.0800 | 2004 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
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