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參數(shù)資料
| 型號： | M2004-31I622.0800LF |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 459K |
| 代理商： | M2004-31I622.0800LF |
M2004-x1 Datasheet Rev 1.1
6 of 12
Revised 16Jul2003
Integr ate d Circuit Systems , In c. ● Comm unication s Modules ● www.icst.com ● tel (508) 852-5400
M2004-X1
FREQUENCY TRANSLATION PLL SERIES
Preliminar y In f o r m atio n
Hitless Switching and Phase Build-out
A proprietary automatic Hitless Switching (HS) function
is included in the M2004-21, M2004-31, M2004-41, and
M2004-51. The HS function provides SONET/SDH
MTIE and TDEV compliance during a reference clock
reselection when using the internal mux. Two variants
are additionally triggered by reference clock reselection
when using an external mux (through detection of the
resulting phase transient).* A Phase Build-out (PBO)
function is also incorporated to absorb most of the
phase change in the reference clock input.
The combined HS/PBO function is armed after the
device locks to the input clock reference. Once armed,
HS/PBO is triggered according to device variant as
follows:
In the M2004-21, M2004-41 and M2004-51, HS/PBO
is only triggered by changing REF_SEL to switch the
input reference clock.
In the M2004-31, HS/PBO is triggered by either
changing REF_SEL or by detection at the phase
detector of an input phase transient beyond 4 ns.
Once triggered, the HS function narrows loop band-
width to control MTIE during locking to the new input
phase.** With proper configuration of the external loop
filter, the output clocks will comply with MTIE and TDEV
specifications for GR-253 (SONET) and ITU G.813
(SDH) during input reference clock changes.
The Phase Build-out (PBO) function enables the PLL to
absorb most of the phase change of the input clock.
The PBO function selects a new VCSO clock edge for
the phase detector feedback clock, selecting the edge
closest in phase to the new input clock phase. This
reduces re-lock time, the generation of wander, and
extra output clock cycles.
When the PLL locks to within 2 ns of the input clock
phase, the PLL returns to normal loop bandwidth and
the HS/PBO function is re-armed.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M2004-x1 requires the use of an
external loop filter components. These are connected to
the provided filter pins (see Figure 5). Due to the
differential signal path design, the implementation
consists of two identical complementary RC filters as
shown in Figure 5, below.
Figure 5: External Loop Filter
PLL bandwidth is affected by the “M” value as well as
the VCSO frequency. See Table 10, External Loop Filter
In addition, loop bandwidth is affected by the Fixed
Narrow Loop Bandwidth (Fixed NBW) feature. See
Fixed Narrow Loop Bandwidth (Fixed NBW) ***
A fixed Narrow Loop Bandwidth feature (Fixed NBW) is
included in the M2004-21, M2004-31, and M2004-51.
These device variants have a narrower loop bandwidth
than the other variants. The internal resistor Rin is
2016 M
, increased from 16 k. This lowers the loop
bandwidth by a factor of 125 (2 / 0.016) and lowers the
damping factor by a factor of 11.18 (the square root of
125), using the same loop components.
PLL Simulator Tool Available
*
Transient-triggered HS/PBO is not suitable for use with an
unstable reference clock that would induce phase jitter beyond
2 ns at the phase detector (e.g., Stratum DPLL clock sources and
unstable recovered network clocks intended for loop timing
configuration). Therefore, all of the HS/PBO devices offer the
internal mux-triggered HS/PBO capability.
** In the M2004-31 and M2004-51, the Fixed NBW function
permanently enables narrow bandwidth, therefore PBO is the
only actively-triggered function.
*** The M2004-01, M2004-11, and M2004-41 do not include
Fixed NBW.
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
相關PDF資料 |
PDF描述 |
|---|---|
| M2004-21I622.0800 | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-51-622.0800 | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-21-622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-31I622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-21I622.0800 | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
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