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參數(shù)資料
| 型號(hào)： | M2004-21I622.0800 |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 459K |
| 代理商： | M2004-21I622.0800 |
M2004-x1 Datasheet Rev 1.1
5 of 12
Revised 16Jul2003
M2004-X1
FREQUENCY TRANSLATION PLL SERIES
Preliminar y In f o r m atio n
Pin Configuration M and N Dividers
The M2004-x1 can be pin-configured with the input pins
M0 - M5
, N0, and N1. Pin configuration of dividers is
enabled when nP_LOAD is LOW. The data on pins M5:0
and pins N1:0 is passed transparently (directly) to the M
and N dividers.
On the LOW-to-HIGH (rising edge) transition of the
nP_LOAD
input, the data is latched.
With nP_LOAD set HIGH, the pin-configured values
remain loaded in the M and N dividers; the dividers are
unaffected by any change to the M5:0 or N1:0 inputs. As a
result, the M5:0 and N1:0 pins can be used to set the
power-up default values for M and N. (The dividers are
also unaffected by any S_DATA serial input as long as
there is no rising edge transition of S_LOAD.)
Serial Programming of M and N Dividers
The M2004-x1 is serially programmed with S_DATA,
S_CLOCK
, and S_LOAD.
Serial input mode is enabled when nP_LOAD is HIGH and
S_LOAD
is LOW (at point “a” in the the timing diagram,
into the configuration shift register with each rising edge
of the S_CLOCK input. (The T1 bit is input first, M0 last.)
When the shift register is full, its entire contents is
loaded in parallel into the M and N dividers. This occurs
on the rising edge of the S_LOAD input (at point “b” in the
timing diagram). This load is transparent; the dividers
immediately contain the serially programmed values.
If S_LOAD is held HIGH, any S_DATA input is passed
transparently (directly) to the M and N dividers on
each rising edge of S_CLOCK.
Serial Configuration Timing Diagram
Figure 4: Serial Configuration Timing Diagram
Pin Configuration & Serial Programming Functions
L = Low; H = High; X = Don't care;
= Rising Edge Transition;
= Falling Edge Transition
Pins
Function
MR
nP_LOAD
M5:0
N1:0
S_LOAD
S_CLOCK
S_DATA
H
X
Resets the dividers and forces FOUT to LOW and nFOUT to HIGH.
Pin Configuration of M and N Dividers
L
Data
X
Data on M5:0 and N1:0 input pins is passed directly (and become
immediately transparent) to the M and N dividers respectively.
L
Data
L
X
Data is latched into M and N dividers and remains loaded until
next HIGH-to-LOW transition of nP_LOAD or a serial load occurs.
Serial Programming of M and N Dividers
L
H
X
L
Data
Serial input mode. Data on the S_DATA pin is serially loaded into
the shift register on each rising clock of S_CLOCK. (However,
serial input does not affect the values in the M and N dividers.)
L
H
X
L
Data
Entire contents of the shift register are passed (and become
immediately transparent) to the M and N dividers.
L
H
X
L
Data
M and N divider values are latched.
L
H
X
L
X
Serial input does not affect the values in the M and N dividers.
LH
X
H
Data
Serial input affects dividers: S_DATA passed directly to M and N
dividers as it is clocked.
S_DATA
S_CLOCK
S_LOAD
a
T1
T0
Null
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
Points a, b, and c referred to in “Serial Programming of M and N Dividers” description above.
The T1 bit is loaded first, M0 last.
b c
相關(guān)PDF資料 |
PDF描述 |
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| M2004-51-622.0800 | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-21-622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-31I622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-21I622.0800 | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
| M2004-31-622.0800LF | PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC36 |
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