2-70 Revision 13 Input Register Timing Characteristics 1.5 V DC Core Voltage Figur" />
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  • 參數(shù)資料
    型號: M1AGLE3000V5-FG896I
    廠商: Microsemi SoC
    文件頁數(shù): 150/166頁
    文件大?。?/td> 0K
    描述: IC FPGA 1KB FLASH 3M 896-FBGA
    標(biāo)準(zhǔn)包裝: 27
    系列: IGLOOe
    邏輯元件/單元數(shù): 75264
    RAM 位總計: 516096
    輸入/輸出數(shù): 620
    門數(shù): 3000000
    電源電壓: 1.425 V ~ 1.575 V
    安裝類型: 表面貼裝
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 896-BGA
    供應(yīng)商設(shè)備封裝: 896-FBGA(31x31)
    IGLOOe DC and Switching Characteristics
    2-70
    Revision 13
    Input Register
    Timing Characteristics
    1.5 V DC Core Voltage
    Figure 2-28 Input Register Timing Diagram
    50%
    Preset
    Clear
    Out_1
    CLK
    Data
    Enable
    t
    ISUE
    50%
    t
    ISUD
    t
    IHD
    50%
    t
    ICLKQ
    1
    0
    t
    IHE
    t
    IRECPRE
    t
    IREMPRE
    t
    IRECCLR
    t
    IREMCLR
    t
    IWCLR
    t
    IWPRE
    t
    IPRE2Q
    t
    ICLR2Q
    t
    ICKMPWH tICKMPWL
    50%
    Table 2-123 Input Data Register Propagation Delays
    Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
    Parameter
    Description
    Std.
    Units
    tICLKQ
    Clock-to-Q of the Input Data Register
    0.42
    ns
    tISUD
    Data Setup Time for the Input Data Register
    0.47
    ns
    tIHD
    Data Hold Time for the Input Data Register
    0.00
    ns
    tISUE
    Enable Setup Time for the Input Data Register
    0.67
    ns
    tIHE
    Enable Hold Time for the Input Data Register
    0.00
    ns
    tICLR2Q
    Asynchronous Clear-to-Q of the Input Data Register
    0.79
    ns
    tIPRE2Q
    Asynchronous Preset-to-Q of the Input Data Register
    0.79
    ns
    tIREMCLR
    Asynchronous Clear Removal Time for the Input Data Register
    0.00
    ns
    tIRECCLR
    Asynchronous Clear Recovery Time for the Input Data Register
    0.24
    ns
    tIREMPRE
    Asynchronous Preset Removal Time for the Input Data Register
    0.00
    ns
    tIRECPRE
    Asynchronous Preset Recovery Time for the Input Data Register
    0.24
    ns
    tIWCLR
    Asynchronous Clear Minimum Pulse Width for the Input Data Register
    0.19
    ns
    tIWPRE
    Asynchronous Preset Minimum Pulse Width for the Input Data Register
    0.19
    ns
    tICKMPWH
    Clock Minimum Pulse Width HIGH for the Input Data Register
    0.31
    ns
    tICKMPWL
    Clock Minimum Pulse Width LOW for the Input Data Register
    0.28
    ns
    Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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