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參數(shù)資料
| 型號(hào)： | M1AGL600V5-CSG281I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 58/250頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1KB FLASH 600K 281-CSP |
| 標(biāo)準(zhǔn)包裝： | 184 |
| 系列： | IGLOO |
| 邏輯元件/單元數(shù)： | 13824 |
| RAM 位總計(jì)： | 110592 |
| 輸入/輸出數(shù)： | 215 |
| 門(mén)數(shù)： | 600000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 281-TFBGA，CSBGA |
| 供應(yīng)商設(shè)備封裝： | 281-CSP（10x10） |
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Pin Descriptions
3-2
Revision 23
VJTAG
JTAG Supply Voltage
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank
gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG
interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to
GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is
insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can
be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals
will not be able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
VPUMP
Programming Supply Voltage
IGLOO devices support single-voltage ISP of the configuration flash and FlashROM. For programming,
VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be
tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply
voltage (VPUMP) range is listed in the datasheet.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 F and 0.33 F capacitors (both rated at 16 V) are to be connected in
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed
GL
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power
Flash Devices and Mixed Signal FPGAs" chapter of the IGLOO FPGA Fabric User’s Guide. All inputs
labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input,
GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are
direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to
the global network are multiplexed, and only one input can be used as a global input.
Refer to the "I/O Structures in IGLOO and ProASIC3 Devices" chapter of the IGLOO FPGA Fabric User’s
Guide for an explanation of the naming of global pins.
FF
Flash*Freeze Mode Activation Pin
Flash*Freeze mode is available on IGLOO devices. The FF pin is a dedicated input pin used to enter and
exit Flash*Freeze mode. The FF pin is active low, has the same characteristics as a single-ended I/O,
and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the
FF pin is available as a regular I/O.
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| M1AGL600V5-CS281I | IC FPGA 1KB FLASH 600K 281-CSP |
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| M1AGL600V5-FCS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| M1AGL600V5-FCS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| M1AGL600V5-FCS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| M1AGL600V5-FCS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| M1AGL600V5-FCSG144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
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