IGLOO Low Power Flash FPGAs
II
Revision 23
I/Os Per Package1
IGLOO Devices
AGL0152 AGL030 AGL060 AGL125
AGL250
AGL400
AGL600
AGL1000
ARM-Enabled
IGLOO Devices
M1AGL250
M1AGL600
M1AGL1000
Package
I/O Type3
Si
ng
le
-End
ed
I/
O
Si
ng
le
-End
ed
I/
O
Si
ng
le
-End
ed
I/
O
Si
ng
le
-End
ed
I/
O
Si
ng
le
-End
ed
I/
O
4
Dif
ferenti
al
I/O
Pairs
Si
ng
le
-End
ed
I/
O
4
Dif
ferenti
al
I/O
Pairs
Si
ng
le
-End
ed
I/
O
4
Dif
ferenti
al
I/O
Pairs
Si
ng
le
-End
ed
I/
O
4
Dif
ferenti
al
I/O
Pairs
QN48
–34
–
QN68
49
–
UC81
–66
–
CS81
–66
–
60
7
–
CS121
––
96
–
VQ100
–77
71
68
13
–
QN132
–81
80
84
87 5,6
19 5,6
––
–
CS196
––
–
133
143 5
35 5
143
35
–
FG144
––
96 7
97
24
97
25
97
25
97
25
FG2567
–
178
38
177
43
177
44
CS281
–
215
53
215
53
FG4847
–
194
38
235
60
300
74
Notes:
ensure compliance with design and board migration requirements.
2. AGL015 is not recommended for new designs.
3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-
ended user I/Os available is reduced by one.
4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
5. The M1AGL250 device does not support QN132 or CS196 packages.
6. Device/package support TBD.
7. FG256 and FG484 are footprint-compatible packages.
Table 1 IGLOO FPGAs Package Sizes Dimensions
Package
UC81
CS81
CS121 QN48 QN68
QN132 CS196
CS281
FG144
VQ100
FG256
FG484
Length × Width
(mm\mm)
4 × 4
5 × 5
6 × 6
8 × 8
10 × 10 13 × 13 14 × 14 17 × 17 23 × 23
Nominal Area
(mm2)
16
25
36
64
100
169
196
289
529
Pitch (mm)
0.4
0.5
0.4
0.5
1.0
0.5
1.0
Height (mm)
0.80
0.99
0.90
0.75
1.20
1.05
1.45
1.00
1.60
2.23