Fusion Family of Mixed Signal FPGAs
Revision 4
2-181
Table 2-106 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI = 3.0 V
Applicable to Advanced I/Os
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
4 mA
Std.
0.66
10.26
0.04
1.20
0.43
10.45
8.90
2.64
2.46
12.68 11.13
ns
–1
0.56
8.72
0.04
1.02
0.36
8.89
7.57
2.25
2.09
10.79
9.47
ns
–2
0.49
7.66
0.03
0.90
0.32
7.80
6.64
1.98
1.83
9.47
8.31
ns
8 mA
Std.
0.66
7.27
0.04
1.20
0.43
7.41
6.28
2.98
3.04
9.65
8.52
ns
–1
0.56
6.19
0.04
1.02
0.36
6.30
5.35
2.54
2.59
8.20
7.25
ns
–2
0.49
5.43
0.03
0.90
0.32
5.53
4.69
2.23
2.27
7.20
6.36
ns
12 mA
Std.
0.66
5.58
0.04
1.20
0.43
5.68
4.87
3.21
3.42
7.92
7.11
ns
–1
0.56
4.75
0.04
1.02
0.36
4.84
4.14
2.73
2.91
6.74
6.05
ns
–2
0.49
4.17
0.03
0.90
0.32
4.24
3.64
2.39
2.55
5.91
5.31
ns
16 mA
Std.
0.66
5.21
0.04
1.20
0.43
5.30
4.56
3.26
3.51
7.54
6.80
ns
–1
0.56
4.43
0.04
1.02
0.36
4.51
3.88
2.77
2.99
6.41
5.79
ns
–2
0.49
3.89
0.03
0.90
0.32
3.96
3.41
2.43
2.62
5.63
5.08
ns
24 mA
Std.
0.66
4.85
0.04
1.20
0.43
4.94
4.54
3.32
3.88
7.18
6.78
ns
–1
0.56
4.13
0.04
1.02
0.36
4.20
3.87
2.82
3.30
6.10
5.77
ns
–2
0.49
3.62
0.03
0.90
0.32
3.69
3.39
2.48
2.90
5.36
5.06
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on