Fusion Family of Mixed Signal FPGAs
Revision 4
2-115
Standard Conversion
Intra-Conversion
Notes:
3. Minimum time to issue an ADCSTART after DATAVALID is 1 SYSCLK period
Figure 2-91 Standard Conversion Status Signal Timing Diagram
SYSCLK
ADCSTART
BUSY
SAMPLE
DATAVALID
t
HDADCSTART
t
SUADCSTART
t
CK2QBUSY
t
CK2QSAMPLE
t
CK2QVAL
t
SAMPLE1
t
CONV
2
ADC_RESULT[11:0]
t
CLK2RESULT
1
st Sample Result
t
CK2QVAL
2
nd Sample Result
t
DATA2START
3
Note: *tCONV represents the conversion time of the second conversion. See EQ 23 on page 2-112 for calculation of the conversion time, tCONV.
Figure 2-92 Intra-Conversion Timing Diagram
SYSCLK
ADCSTART
BUSY
SAMPLE
DATAVALID
t
CK2QSAMPLE
t
CK2QSAMPLE
tCK2QVAL
t
CONV*
t
CLR2QVAL
t
CK2QBUSY
ADCRESET
CALIBRATE
t
CK2QCAL
tCK2QCAL
Interrupts Power-Up Calibration
Resumes Power-Up Calibration