- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4387 > M1A3PE3000-PQG208 (Microsemi SoC)IC FPGA 1KB FLASH 3M 208-PQFP PDF資料下載
參數(shù)資料
| 型號： | M1A3PE3000-PQG208 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 60/162頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1KB FLASH 3M 208-PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | ProASIC3E |
| RAM 位總計(jì)： | 516096 |
| 輸入/輸出數(shù)： | 147 |
| 門數(shù)： | 3000000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁當(dāng)前第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁
Datasheet Information
5-2
Revision 13
Revision 11
(continued)
Figure 2-11 AC Loading was updated to match tables in the "Summary of I/O
In Table 2-81 Minimum and Maximum DC Input and Output Levels, VIL and VIH
were revised so that the maximum is 3.6 V for all listed values of VCCI (SAR
37222).
Figure 2-47 FIFO Read and Figure 2-48 FIFO Write are new (SAR 34848).
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)"
section in the "Pin Descriptions and Packaging" chapter: "Within the package, the
VMV plane is decoupled from the simultaneous switching noise originating from
the output buffer VCCI domain" and replaced with “Within the package, the VMV
plane biases the input stage of the I/Os in the I/O banks” (SAR 38322). The
datasheet mentions that "VMV pins must be connected to the corresponding
VCCI pins" for an ESD enhancement.
Revision 10
(March 2012)
were revised to clarify that although no existing security measures can give an
absolute guarantee, Microsemi FPGAs implement the best security available in
the industry (SAR 34669).
The Y security option and Licensed DPA Logo were added to the "ProASIC3E
Ordering Information" section. The trademarked Licensed DPA Logo identifies
that a product is covered by a DPA counter-measures license from Cryptography
Research (SAR 34727).
The following sentence was removed from the "Advanced Architecture" section:
"In addition, extensive on-chip programming circuitry allows for rapid, single-
voltage (3.3 V) programming of IGLOOe devices via an IEEE 1532 JTAG
interface" (SAR 34689).
The "Specifying I/O States During Programming" section is new (SAR 34699).
VCCPLL in Table 2-2 Recommended Operating Conditions 1 was corrected
from "1.4 to 1.6 V" to "1.425 to 1.575 V" (SAR 33851).
The TJ symbol was added to the table and notes regarding TA and TJ were
removed. The second of two parameters in the VCCI and VMV row, called "3.3 V
DC supply voltage," was corrected to "3.0 V DC supply voltage" (SAR 37227).
The reference to guidelines for global spines and VersaTile rows, given in the
"Global Clock Contribution—PCLOCK" section, was corrected to t
he "Spine
Architecture" section of the Global Resources chapter in the ProASIC3E
FPGA Fabric User's Guide (SAR 34735).
(example) (SAR 37109).
The typo related to the values for 3.3 V LVCMOS Wide Range in Table 2-17
corrected (SAR 37227).
The notes regarding drive strength in the "Summary of I/O Timing Characteristics
section and tables were revised for clarification. They now state that the minimum
drive strength for the default software configuration when run in wide range is
±100 A. The drive strength displayed in software is supported in normal range
only. For a detailed I/V curve, refer to the IBIS models (SAR 34763).
Revision
Changes
Page
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A3PE3000-PQ208 | IC FPGA 1KB FLASH 3M 208-PQFP |
| 5CGXFC7C7U19C8NES | IC CYCLONE V FPGA 150K 484-UBGA |
| ASC12DTES | CONN EDGECARD 24POS .100 EYELET |
| AMC12DTES | CONN EDGECARD 24POS .100 EYELET |
| EP4CGX75DF27C6 | IC CYCLONE IV GX FPGA 75K 672FBG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1A3PE3000-PQG208I | 功能描述:IC FPGA 1KB FLASH 3M 208-PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3E 標(biāo)準(zhǔn)包裝:1 系列:ProASICPLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):129024 輸入/輸出數(shù):248 門數(shù):600000 電源電壓:2.3 V ~ 2.7 V 安裝類型:表面貼裝 工作溫度:- 封裝/外殼:352-BFCQFP，帶拉桿 供應(yīng)商設(shè)備封裝:352-CQFP（75x75） |
| M1A3PE3000-PQG896 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| M1A3PE3000-PQG896ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| M1A3PE3000-PQG896I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| M1A3PE3000-PQG896PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。