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| 型號(hào)： | M1A3P400-FFG144 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA144 |
| 封裝： | 13X 13 MM, 1.45 MM HEIGHT, 1 MM PITCH, FBGA-144 |
| 文件頁(yè)數(shù)： | 2/49頁(yè) |
| 文件大小： | 5893K |
| 代理商： | M1A3P400-FFG144 |
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ProASIC3 DC and Switching Characteristics
v1.3
2 - 83
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-106 ProASIC3 CCC/PLL Specification
Parameter
Minimum
Typical
Maximum
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
350
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
350
MHz
Serial Clock (SCLK) for Dynamic PLL1
125
MHz
Delay Increments in Programmable Delay Blocks2, 3
200
ps
Number of Programmable Values in Each Programmable
Delay Block
32
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network
Used
3 Global
Networks
Used
0.75 MHz to 24 MHz
0.50%
0.70%
24 MHz to 100 MHz
1.00%
1.20%
100 MHz to 250 MHz
1.75%
2.00%
250 MHz to 350 MHz
2.50%
5.60%
Acquisition Time
(A3P250 and A3P1000 only)
LockControl = 0
300
s
LockControl = 1
300
s
(all other dies)
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter 5
(A3P250 and A3P1000 only)
LockControl = 0
1.6
ns
LockControl = 1
1.6
ns
(all other dies)
LockControl = 0
1.6
ns
LockControl = 1
0.8
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 12, 3
0.6
5.56
ns
Delay Range in Block: Programmable Delay 22, 3
0.025
5.56
ns
Delay Range in Block: Fixed Delay2, 3
2.2
ns
Notes:
1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific
junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 for deratings.
3. TJ = 25°C, VCC = 1.5 V
4. The A3P030 device does not contain a PLL.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL
input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by
the period jitter parameter.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M1A3P400-FFG256 | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA256 |
| M1A3P400-FFG484 | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA484 |
| M1A3P400-FFGG144 | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA144 |
| M1A3P400-FFGG256 | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA256 |
| M1A3P400-FFGG484 | FPGA, 9216 CLBS, 400000 GATES, 350 MHz, PBGA484 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M1A3P400-FFG144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-FFG144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-FFG144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-FFGG144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
| M1A3P400-FFGG144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3 Flash Family FPGAs |
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