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參數(shù)資料
| 型號(hào)： | M1A3P1000L-1FGG484 |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA M1 1KB FLASH 1M 484FBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | ProASIC3L |
| RAM 位總計(jì)： | 147456 |
| 輸入/輸出數(shù)： | 300 |
| 門數(shù)： | 1000000 |
| 電源電壓： | 1.14V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 484-BGA |
| 供應(yīng)商設(shè)備封裝： | 484-FPBGA（23x23） |
ARM CortexTM-M1
Prod uct Br ief
9
The processor supports both level and pulse interrupts. A
level interrupt is held asserted until it is cleared by the
ISR accessing the device. A pulse interrupt is a variant of
an edge model. The edge must be sampled on the rising
edge of the processor clock, HCLK, instead of being
asynchronous.
For level interrupts, if the signal is not deasserted before
the return from the interrupt routine, the interrupt
repends and reactivates. This is particularly useful for
FIFO and buffer-based devices because it ensures that
they drain either by a single ISR or by repeated
invocations, with no extra work. This means that the
device holds the signal in assert until the device is empty.
A pulse interrupt can be reasserted during the ISR so that
the interrupt can be pended and active at the same time.
The application design must ensure that a second pulse
does not arrive before the first pulse is activated. If it
does the second pend has no affect because it is already
pended. However, if the interrupt is asserted for at least
one cycle, the NVIC latches the pend bit. When the ISR
activates, the pend bit is cleared. If the interrupt asserts
again while it is activated, it can latch the pend bit again.
Processor Bus Interfaces
As currently available for use in M1 devices, the ARM
Cortex-M1 has an AHB-Lite external interface. The
processor also contains an internal bus called the Private
Peripheral Bus (PPB) for accesses to the Nested Vectored
Interrupt Controller (NVIC), Data Watchpoint (DW) unit,
and BreakPoint (BPU), but this is not directly accessible to
the user.
External Interface
The external interface is an AHB-Lite bus interface. The
processor accesses to AHB peripherals and memory are
implemented over this bus.
To prevent bus wait cycles from stalling the processor
during data stores, buffered stores to the external
interface go through a one-entry write buffer. If the
write buffer is full, subsequent accesses to the bus stall
until the write buffer has drained. The write buffer is
only used if the bus waits for the data phase of the
buffered store; otherwise, the transaction completes on
the bus.
Memory Interfaces
The tightly coupled memory interface defined in the
ARM Cortex-M1 architecture is not currently supported
on M1 devices. Future core releases will have support for
this memory interface.
Private Peripheral Bus
The AHB PPB is used to access the Nested Vector
Interrupt Controller and the debug components when
they are present. The PPB allows communication to flow
between the AHB and NVIC units and the debug circuitry
when it is implemented in the core.
Delivery and Deployment
ARM Cortex-M1 is delivered as a series of files by
CoreConsole that are directly imported into the Design
and Simulation folders by Libero IDE. These consist of the
BFM files and test wrapper, and the A1S secured CDB file,
which is the placed-and-routed ARM Cortex-M1 core,
actually instantiated on the user device. This deployment
flow is adopted to ensure that the design is kept
completely secure at all times.
Initially, the ARM Cortex-M1 processor is being made
available for use in Actel M1 devices with only one user
selectable option: with or without debug. The core is
configured with 0K ITCM, 0K DTCM, small multiplier,
little-endian, no OS extensions, and 1 interrupt.
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| M1A3P1000L-1FGG484I | 功能描述:IC FPGA M1 1KB FLASH 1M 484FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3L 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23） |
| M1A3P1000L-1PQ208 | 功能描述:IC FPGA M1 1KB FLASH 1M 208PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3L 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| M1A3P1000L-1PQ208I | 功能描述:IC FPGA M1 1KB FLASH 1M 208PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3L 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| M1A3P1000L-1PQG208 | 功能描述:IC FPGA M1 1KB FLASH 1M 208PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3L 標(biāo)準(zhǔn)包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計(jì):36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
| M1A3P1000L-1PQG208I | 功能描述:IC FPGA M1 1KB FLASH 1M 208PQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3L 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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