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參數(shù)資料
| 型號： | M1A3P1000L-1FG256I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 2/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA M1 1KB FLASH 1M 256FBGA |
| 標準包裝： | 90 |
| 系列： | ProASIC3L |
| RAM 位總計： | 147456 |
| 輸入/輸出數(shù)： | 177 |
| 門數(shù)： | 1000000 |
| 電源電壓： | 1.14V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 256-LBGA |
| 供應(yīng)商設(shè)備封裝： | 256-FPBGA（17x17） |
ARM CortexTM-M1
10
Prod uct Bri e f
Bus Functional Model (BFM)
Introduction
During the development of an FPGA-based SoC, there
are various stages of testing that can be undertaken. This
can involve some, or all, of the following approaches:
Hardware simulation using Verilog or VHDL
Software simulation using a host-based instruction
set simulator (ISS) of the SoC’s processor
Hardware and software co-verification using a
full-functional model of the processor in Verilog,
VHDL or SWIFT form, or using a tool such as
Seamless
BFM Usage Flow
The BFM acts as a pin-for-pin replacement of the
Cortex-M1 in the simulation of the SoC subsystem. It
initiates bus transactions on the native ARM Cortex-M1
bus, which are cycle-accurate with real bus cycles that
ARM Cortex-M1 would produce. It does not have the
ability, however, to implement real ARM Cortex-M1
instructions. The BFM may be used to run a basic test
suite of the SoC subsystem, using the skeleton system
testbench.
You can edit the SoC Verilog/VHDL to add new design
blocks. You can also fill out the system-level testbench to
include tasks that test any newly added functionality, or
add stubs to allow more complex system testing
involving the IP cores. The BFM input scripts can also be
manually enhanced to test out access to register
locations in newly added logic. In this way, you can
provide stimuli to the system from the inside (via the
ARM Cortex-M1 BFM), as well as from the outside (via
testbench tasks).
Timing Shell
There is a timing shell provided for each ARM Cortex-M1
variant wrapped around the BFM. Therefore, the BFM is
bus cycle accurate, and performs setup/hold checks to
model output propagation delays.
Debug
The ARM Debug Architecture uses a protocol converter
box to allow the debugger to talk directly to the core via
a JTAG port. In effect, the scan chains in the core that are
required for test are re-used for debugging. The core
uses the scan chains to insert instructions directly into
ARM Cortex-M1. The instructions are executed on the
core and depending on the type of instruction that has
been inserted, the core or the system state can be
examined, saved, or changed. The architecture has the
ability to execute instructions at a slow debug speed or
to execute instructions at system speed.
In debug mode, the user can perform the following
functions:
Core halt
Core stepping
Core register access
Read/Write to TCMs
Read/Write to AHB address space
Breakpoint
Watchpoints
The main debug components are the following:
Debug control registers – to access and control
debugging of the core
Breakpoint Unit (BPU) – to implement breakpoints
Data Watchpoint Unit (DW) – to implement
watchpoints and trigger resources
Debug memory interfaces – to access external
ITCM and DTCM
ROM table
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| M1A3P1000L-1FG484 | 功能描述:IC FPGA M1 1KB FLASH 1M 484FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3L 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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| M1A3P1000L-1FGG144 | 功能描述:IC FPGA M1 1KB FLASH 1M 144FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3L 標準包裝:90 系列:ProASIC3 LAB/CLB數(shù):- 邏輯元件/單元數(shù):- RAM 位總計:36864 輸入/輸出數(shù):157 門數(shù):250000 電源電壓:1.425 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 125°C 封裝/外殼:256-LBGA 供應(yīng)商設(shè)備封裝:256-FPBGA（17x17） |
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