
Bus
39
Mitsubishi microcomputers
M16C / 62P Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
development
Preliminary Specifications Rev.1.0
Specifications in this manual are tentative and subject to change.
Processor mode
Memory expansion mode or microprocessor mode
00
2
(separate bus)
Memory expansion
mode
11
2
(multiplexed bus
for the entire space)
(Note 1)
PM05–PM04 bits
01
2
(CS2 is for multiplexed bus and
others are for separate bus)
10
2
(CS1 is for multiplexed bus and
others are for separate bus)
Data bus width
8 bits
“H”
BYTE pin
P0
0
to P0
7
D
0
to D
7
D
0
to D
7
D
0
to D
7
D
0
to D
7
I/O ports
P1
0
to P1
7
I/O ports
D
8
to D
15
I/O ports
D
8
to D
15
I/O ports
P2
0
A
0
A
0
A
0
/D
0
(Note 2)
A
1
to A
7
/D
1
to D
7
(Note 2)
A
0
A
1
to A
7
/D
0
to D
6
(Note 2)
A
0
/D
0
A
1
to A
7
/D
1
to D
7
P2
1
to P2
7
A
1
to A
7
A
1
to A
7
P3
0
A
8
A
8
A
8
A
8
/D
7
(Note 2)
A
8
P3
1
to P3
3
A
9
to A
11
I/O ports
P3
4
to P3
7
A
12
to A
15
I/O ports
P4
0
to P4
3
A
16
to A
19
I/O ports
P4
4
I/O ports
P4
5
P4
6
P4
7
P5
0
WRL
P5
2
RD
P5
3
BCLK
P5
4
HLDA
P5
5
HOLD
ALE
P5
6
P5
7
RDY
PM11=0
PM11=1
I/O ports
PM06=0
PM06=1
CS0=0
I/O ports
CS0=1
CS0
I/O ports
CS1=0
CS1=1
CS1
I/O ports
CS2=0
CS2=1
CS2
I/O ports
CS3=0
CS3=1
CS3
WR
PM02=0
PM02=1
(Note 3)
WRL
(Note 3)
(Note 3)
P5
1
BHE
WRH
PM02=0
PM02=1
(Note 3)
WRH
(Note 3)
(Note 3)
Note 1: To set the PM01 to PM00 bits are set to “01
2
” and the PM05 to PM04 bits are set to “11
2
” (multiplexed bus assigned to the entire CS
space), apply “H” to the BYTE pin (external data bus 8 bits wide). While the CNV
SS
pin is held “H” (= V
CC1
), do not rewrite the PM05
to PM04 bits to “11
2
” after reset. If the PM05 to PM04 bits are set to “11
2
” during memory expansion mode, P3
1
to P3
7
and P4
0
to P4
3
become I/O ports, in which case the accessible area for each CS is 256 bytes.
Note 2: In separate bus mode, these pins serve as the address bus.
Note 3: If the data bus is 8 bits wide, make sure the PM02 bit is set to “0” (RD, BHE, WR).
I/O ports: Function as I/O ports or peripheral function I/O pins.
8 bits
“H”
8 bits
“H”
16 bits
“L”
16 bits
“L”
Table 1.7.5. Pin Functions for Each Processor Mode