Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timing (Vcc = 5V)
182
Switching characteristics (referenced to V
CC
= 5V, V
SS
= 0V at Topr =
–
20
o
C to 85
o
C /
–
40
o
C to
85
o
C (Note 2), CM15 =
“
1
”
unless otherwise specified)
V
CC
= 5V
Table 1.23.22. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Symbol
Standard
Min.
Measuring condition
Max.
25
Parameter
Unit
t
d(BCLK-AD)
t
h(BCLK-AD)
t
h(RD-AD)
t
h(WR-AD)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
ns
ns
ns
ns
4
t
d(BCLK-CS)
t
h(BCLK-CS)
t
h(RD-CS)
t
h(WR-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
25
ns
ns
ns
ns
4
(Note1)
t
d(BCLK-RD)
t
h(BCLK-RD)
t
d(BCLK-WR)
t
h(BCLK-WR)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
25
ns
ns
ns
ns
0
(Note1)
25
t
d(BCLK-DB)
t
h(BCLK-DB)
t
d(DB-WR)
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
40
ns
ns
ns
4
(Note1)
t
d(BCLK-ALE)
t
h(BCLK-ALE)
t
d(AD-ALE)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (Address standard)
25
ns
ns
ns
– 4
(Note1)
t
h(ALE-AD)
t
d(AD-RD)
t
d(AD-WR)
t
dZ(RD-AD)
Note 1: Calculated according to the BCLK frequency as follows:
10
9
ALE signal output hold time (Adderss standard)
Post-address RD signal output delay time
Post-address WR signal output delay time
Address output floating start time
30
0
0
ns
ns
ns
ns
0
(Note1)
(Note1)
8
t
h(WR-DB)
Data output hold time (WR standard)
ns
(Note1)
th(RD – AD) =
f(BCLK) X 2
[ns]
th(WR – AD) =
f(BCLK) X 2
10
9
[ns]
th(RD – CS) =
f(BCLK) X 2
10
9
[ns]
th(WR – CS) =
f(BCLK) X 2
10
9
[ns]
td(DB – WR) =
f(BCLK) X 2
10
9
– 40
[ns]
X 3
td(AD – ALE) =
f(BCLK) X 2
10
9
– 25
[ns]
th(WR – DB) =
f(BCLK) X 2
10
9
[ns]
Note 2: Specify a product of -40°C to 85°C to use it.
Figure 1.23.1