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| 型號(hào)： | M1033-16I167.3316 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | 1033 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大?。?/td> | 200K |
| 代理商： | M1033-16I167.3316 |
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M1033/34 Preliminary Information 0.1
12 of 14
Revised 07Apr2005
I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0
Integrated
Circuit
Systems, Inc.
M1033/34
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminar y In f o r m atio n
ELECTRICAL SPECIFICATIONS (CONTINUED)
PARAMETER MEASUREMENT INFORMATION
Output Rise and Fall Time
Figure 6: Output Rise and Fall Time
Output Duty Cycle
Figure 7: Output Duty Cycle
AC Characteristics
Unless stated otherwise, V
CC = 3.3V +5%,TA = 0
oC to +70 oC (commercial), T
A = -40
oC to +85 oC (industrial), F
VCSO = FOUT = 150-175MHz,
LVPECL outputs terminated with 50
to V
CC - 2V
Symbol Parameter
Min
Typ
Max
Unit Conditions
F
IN
Input Frequency
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
15
700
MHz
F
OUT
Output Frequency
FOUT, nFOUT
62.5
175
MHz
APR
Absolute Pull-Range
of VCSO
Commercial
±120
±200
ppm
Industrial
±50
±150
ppm
PLL Loop
Constants 1
Note 1: Parameters needed for PLL Simulator software; see Table 7, Example External Loop Filter Component Values, on pg. 9.
K
VCO
VCO Gain
200
kHz/V
R
IN
Internal Loop Resistor
Wide Bandwidth
100
k
Narrow Bandwidth
2100
k
BW
VCSO
VCSO Bandwidth
700
kHz
Phase Noise
and Jitter
Φn
Single Side Band
Phase Noise
@155.52MHz
1
kHz Offset
-83
dBc/Hz Fin=19.44 or
38.88_MHz
Tot. PLL ratio = 8
or 4. See pg. 3
10
kHz Offset
-113
dBc/Hz
100
kHz Offset
-136
dBc/Hz
J(t)
Jitter (rms)
@155.52MHz
12
kHz to 20MHz
0.4
0.6
ps
odc
Output Duty Cycle 2
Note 2: See Parameter Measurement Information on pg. 12.
45
50
55
%
t
R
Output Rise Time 2
for FOUT, nFOUT
350
450
550
ps
20
% to 80%
t
F
Output Fall Time 2
for FOUT, nFOUT
350
450
550
ps
20
% to 80%
Table 11: AC Characteristics
20%
80%
tR
20%
tF
80%
Clock Output
V
P
-P
nFOUT
FOUT
t
PW
t
PERIOD
(Output Pulse Width)
tPERIOD
tPW
odc =
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