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參數(shù)資料
| 型號： | M1033-16-161.1328 |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 1033 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 |
| 封裝： | 9 X 9 MM, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大?。?/td> | 200K |
| 代理商： | M1033-16-161.1328 |
M1033/34 Preliminary Information 0.1
8 of 14
Revised 07Apr2005
I n te g r at ed Ci rcui t Systems , In c. ● N e tw o r ki ng & Co mmun ica t io ns ● ww w. icst.co m ● tel (5 08 ) 85 2-5 4 0 0
Integrated
Circuit
Systems, Inc.
M1033/34
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Preliminar y In f o r m atio n
Optional Phase Build-out Feature (PBOM)
The M1033/34 is available with a proprietary Phase
Build-out feature. The Phase Build-out (PBOM) function
enables the PLL to absorb most of the phase change of
the input clock whenever an input reference reselection
occurs. PBOM is triggered only by a change of state of
the input reference selection mux.
PBOM identifies the unique “Phase Build-out only
upon MUX reselection” feature of the M1035/36
devices. Other M1000 series devices use the PBO
circuit that is triggered by an input phase transient.
A change of state of the input reference selection mux
can occur through a REF_SEL input change in either
manual or automatic mode; this will be indicated by a
change in state of the REF_ACK output.
In general the two clock references presented to the
M1033/34 will not be phase aligned. They also may not
be the same frequency. Therefore at the time when the
input reference reselection occurs, the PLL will not be
phase locked to the new reference. The PBOM function
selects a new VCSO clock edge for the PLL Phase
Detector feedback clock, selecting the edge closest in
phase to the new input clock phase. This reduces
re-lock time, the generation of wander and extra output
clock cycles. This also results in a phase change
between the selected input reference and the clock
outputs; again the idea of “phase build-out” is to absorb
the phase change of input.
Narrow Bandwidth (NBW) Control Pin
A Narrow Loop Bandwidth control pin (NBW pin) is
included to adjust the PLL loop bandwidth. In wide
bandwidth mode (NBW=0), the internal resistor Rin is
100k
. With the NBW pin asserted, the internal resistor
Rin is changed to 2100k
. This lowers the loop
bandwidth by a factor of about 21 (approximately 2100 /
100) and lowers the damping factor by a factor of about
4.6 (the square root of 21), assuming the same loop
filter components.
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