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參數(shù)資料
| 型號： | M-986-2R2P |
| 廠商： | CLARE INC |
| 元件分類： | 信令電路 |
| 英文描述： | MFC Transceivers |
| 中文描述： | TELECOM, MF SIGNALING CIRCUIT, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 499K |
| 代理商： | M-986-2R2P |
www.clare.com
6
M-986-2A1
Rev. 3
Serial Port Timing
Parameter
Min
-
20
20
244
20
20
399
-
-
220
220
100
Nom
-
-
-
-
-
-
488.28
-
-
244.14
244.14
-
Max
70
-
-
-
-
-
4770
30
30
2500
2500
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
d
(CH-FR)
t
d
(DX1-CL)
t
d
(DX2-CL)
t
h
(DX)
t
su
(DR)
t
h
(DR)
t
c
(SCLK)
t
f
(SCLK)
t
r
(SCLK)
t
w
(SCLKL)
t
w
(SCLKH)
t
su
(FS)
Internal framing delay from SCLK rising edge
DX bit 1 valid before SCLK falling edge
DX bit 2 valid before SCLK falling edge
DX hold time after SCLK falling edge
DR setup time before SCLK falling edge
DR hold time after SCLK falling edge
Serial port clock cycle time
Serial port clock fall time
Serial port clock rise time
Serial port clock low-pulse duration*
Serial port clock high-pulse duration*
FSX/FSR setup time before SCLK falling edge
* The duty cycle of the serial port clock must be within 45% to 55%.
External Frequency Specifications
Parameter
Min
48.818
-
20
Nom
48.828
5
-
Max
48.838
10
-
Unit
ns
ns
ns
t
C
(MC)
t
r
(MC)
t
f
(MC)
Master clock cycle time
Rise time master clock input
Pulse duration master clock
Recommended Operating Conditions
Parameter
Min
4.75
-
2
3
2.2
-
-
-
-
0
Nom
5
0
-
-
-
-
-
-
-
-
Max
5.25
-
-
-
-
0.8
0.6
-300
2
70
Unit
V
V
V
V
V
V
V
μA
mA
C
V
CC
V
SS
V
IH
Supply voltage
Supply voltage
High-level input voltage
All inputs except CLKIN
CLKIN
MC/PM
All inputs except MC/MP
MC/MP
V
IL
Low-level input voltage
I
OH
I
OL
T
A
High-level output current (all outputs)
Low-level output current (all outputs)
Operating free-air temperature
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