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參數(shù)資料
| 型號(hào)： | LZ37C1B |
| 廠商： | SHARP ELECTRONICS CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CQCC36 |
| 封裝： | 0.425 INCH, CERAMIC, LCC-36 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大小： | 123K |
| 代理商： | LZ37C1B |
PRELIMINARY
LZ37C1B
7
TIMING CHART
CLK
ADOUT
(D0-D7)
Normal
HD
CLK
ADOUT
(D0-D7)
906
4
363 365 367 OB
OB
8
12162024283236404448525660646872768084889092
HORIZONTAL PULSE TIMING
PHASE RELATIONS BETWEEN DIGITAL OUTPUT (ADOUT) AND CLOCK (CLK)
VERTICAL PULSE TIMING
ππππππππππππππ
OB ππππππππππππππ
Mirror
75
3
1
OB
CLK
ADOUT
(D0-D7)
Normal
HD
104 108 112 116 120 124 128 132 136 140 144 148 152 156 160 164 168 172 176 180 184 188 192 196 200
OB
2
4
6
8
10
ππππππππππππππ
OB
ππππππππππππππ
Mirror
ADOUT
(D0-D7)
Normal
Mirror
910
HD
SCLK
SDI
AGC
VD
329 330 123456789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SDI, SCLK
Forbidden Period
37 38
OB OB
39
328
289 290 291 OB OB OB OB
288
D0
D10
D20
D30
D38
OB
366 364 362 360 358
SYMBOL
MIN.
TYP.
MAX.
UNIT
t
0
15
40
ns
OB OB
321 OB OB OB OB
4
SERIAL DATA TIMING (SDI, SCLK)
Offset
Shutter
t
01
The rising edge of the HD pulse must be between two rising edges of CLK (0) and CLK (1).
The falling edge of the HD pulse must be between two rising edges of CLK (90) and CLK (91).
The rising edge and falling edge of the VD pulse must be in high period of the HD pulses.
Data in SDI are taken at the rising edge of SCLK.
Clock frequency of SCLK should be less than 1/2 of that of CLK.
Do not insert the SDI and SCLK pulses between 36H* and 37H*. Refer to "VERTICAL PULSE TIMING".
Refer to "SERIAL DATA INPUTS" for the contents of serial data from D0 to D38.
* It means ordinal number of the HD pulse.
361
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