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參數(shù)資料
| 型號： | LZ2413H |
| 廠商： | Sharp Corporation |
| 英文描述： | 1/4-type Color CCD Area Sensors with 270 k Pixels |
| 中文描述： | 1/4-type彩色CCD感應(yīng)器與270萬像素 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大小： | 86K |
| 代理商： | LZ2413H |
3
LZ2413H
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Ambient operating temperature
Output transistor drain voltage
Overflow drain clock
Ground
NOTES :
Connect NC
1
and NC
2
to GND directly or through a capacitor larger than 0.047 μF.
1. Use the circuit parameter indicated in
"SYSTEM CONFIGURATION EXAMPLE"
, and do not connect to DC voltage directly.
2. V
PW
is set below V
VL
that is low level of vertical shift register clock, or is used with the same power supply that is connected
to V
L
of V driver IC.
* To apply power, first connect GND and then turn on V
OD
. After turning on V
OD
, turn on PW first and then turn on other powers
and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.
SYMBOL
T
OPR
V
OD
V
OFD
GND
MIN.
TYP.
25.0
15.0
MAX.
UNIT
C
V
V
V
NOTE
14.55
21.5
15.45
23.5
1
P-well voltage
V
PW
–9.0
V
VL
V
2
0.0
V
–7.5
–8.0
–8.5
V
V1L
, V
V2L
V
V3L
, V
V4L
V
V1I
, V
V2I
V
V3I
, V
V4I
V
V1H
, V
V3H
V
H1L
, V
H2L
V
H1H
, V
H2H
V
RS
f
V1
, f
V2
f
V3
, f
V4
Vertical shift
register clock
LOW level
INTERMEDIATE level
HIGH level
LOW level
HIGH level
p-p level
14.55
–0.05
3.0
3.0
0.0
15.0
0.0
3.3
3.3
15.45
0.05
5.25
5.25
V
V
V
V
V
Horizontal shift
register clock
Reset gate clock
1
Reset gate clock frequency
f
RS
9.53
MHz
Horizontal shift register clock frequency
f
H1
, f
H2
9.53
MHz
Vertical shift register clock frequency
15.73
kHz
p-p level
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