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參數(shù)資料
| 型號： | LZ2325A |
| 廠商： | Sharp Corporation |
| 英文描述： | Dual-power-supply (5 V/12 V) Operation 1/3-type CCD Area Sensors with 320 k Pixels |
| 中文描述： | 雙電源的320萬像素（5 V/12號五）防治荒漠化區(qū)域行動1/3-type傳感器 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 102K |
| 代理商： | LZ2325A |
LZ2325A/LZ2326AR
3
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Ambient operating temperature
Output transistor drain voltage
Reset transistor drain voltage
Overflow drain clock
p-p level
SYMBOL
T
OPR
V
OD
V
RD
V
OFD
MIN.
TYP.
25.0
12.5
V
OD
12.5
MAX.
UNIT
C
V
V
V
NOTE
12.0
13.0
Ground
Test pin, T
1
GND
V
T1
V
TGL
V
TGH
V
V1
, V
V2
V
V3
, V
V4
0.0
V
OD
0.0
12.5
V
V
V
V
Horizontal shift register
clock
LOW level
V
H1L
, V
H2L
V
H1BL
, V
H2BL
V
H1H
, V
H2H
V
H1BH
, V
H2BH
V
RS
f
V1
, f
V2
f
V3
, f
V4
f
H1
, f
H2
f
H1B
, f
H2B
f
RS
tw
1
, tw
2
–0.05
0.0
0.05
V
HIGH level
4.7
5.0
5.5
V
Reset gate clock
p-p level
4.5
Vertical shift register clock frequency
15.63
kHz
Horizontal shift register clock frequency
9.66
MHz
Reset gate clock frequency
Horizontal shift register clock phase
NOTES :
1. Use the circuit parameter indicated in
"SYSTEM CONFIGURATION EXAMPLE"
, and do not connect to DC voltage directly.
2.
9.66
10.0
MHz
ns
1
13.0
12.0
0.05
13.0
–0.05
12.0
Transfer gate clock
LOW level
HIGH level
p-p level
Vertical shift register
clock
4.7
5.0
5.5
V
1
5.0
5.5
V
1
2
18.0
5.0
* To apply power, first connect GND and then turn on V
OD
and then turn on other powers and pulses. Do not connect the
device to or disconnect it from the plug socket while power is being applied.
H1
,
H2
H1B
,
H2B
: Normal image output mode
H1B
,
H2B
: Mirror image output mode
tw
1
tw
2
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