參數(shù)資料
型號(hào)： LZ0P3817
廠商： SHARP ELECTRONICS CORP
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, CQCC36
封裝： 11.40 X 11.40 MM, 7 MM HEIGHT, LCC-36
文件頁(yè)數(shù)： 10/16頁(yè)
文件大?。?/td> 145K
代理商： LZ0P3817
PRELIMINARY
3
LZ0P3817
PIN DESCRIPTION
PIN NO. SYMBOL
I/O
DESCRIPTION
A/D
Analog
Digital ground
–
AVDD
11
Analog
Analog power supply
–
AGND
10
Digital
Analog ground
I
STBY
9
–
Standby control mode*
–
NC
8
Analog
No connection
–
ADH
7
Analog
Top ADC reference voltage
–
ADL
6
Analog
Bottom ADC reference voltage
–
OFS
5
Analog
Offset bias voltage for AGC output
–
AVDD
4
Analog
Analog power supply
–
AGND
3
Analog
Analog ground
O
AGCOUT
2
Analog
AGC output
–
BIAS1
1
Analog bias voltage 1 for image sensor
12
DGND
–
Digital
I
SDI
27
Control data input (AGC gain, offset, shutter control,
image inversion, etc.)
Digital
I
VD
26
Vertical drive pulse input
Digital
I
HD
25
Horizontal drive pulse input
Digital
O
CLK
24
Clock output (6.135 MHz)
Digital
O
D7
23
ADC signal output (MSB)
Digital
O
D6
22
ADC signal output
Digital
O
D5
21
ADC signal output
Digital
O
D4
20
ADC signal output
Digital
O
D1
17
ADC signal output
Digital
O
CKO
15
Clock output for oscillator
Digital
I
CKI
14
Clock input for oscillator (12.27 MHz)
Digital
–
DVDD
13
Digital power supply
Analog bias voltage 2 for image sensor
34
* Standby mode functions
High level : Standby mode (all circuits power-off), Low level or open : Normal mode (all circuits active)
BIAS2
–
Analog
Analog image signal input
33
SIGIN
I
Analog
Analog image signal output
32
SIGOUT
O
Analog
Analog bias voltage 1 for clamp circuit
31
CLP1
–
Analog
Analog bias voltage 2 for clamp circuit
30
CLP2
–
Analog
Load pulse for data input
29
LOAD
I
Digital
Shift clock for data
28
SCLK
I
Digital
ADC signal output (LSB)
16
D0
O
Digital
ADC signal output
18
D2
O
Digital
O
D3
19
ADC signal output
–
NC
36
No connection
Analog
I
REFIN
35
Reference voltage for analog input
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