參數(shù)資料
型號(hào)： LXT9880AHC
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 90/96頁(yè)
文件大?。?/td> 1309K
代理商： LXT9880AHC
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
90
Datasheet
Table 70. Repeater Configuration Register Bit Assignments
31:13
12
11
10
9
8
7
6
5
4
3
2
1:0
Reserved
Enable
Port
Late
Event
Auto
Clear
Stats
Enable
Send
/T/R
Iso
100
Iso
10
Uni-cast
Frame
Count
Arbit
Input
Value
Zero
Cntrs
Enable
FIFO
Error
Enable
Manchst
r Code
Violation
Reserved
Table 71. Repeater Configuration Register Bit Definitions
Bit
Name
Type
1
Description
Default
31:13
Reserved
R/W
Reserved - Write as
‘
0s; ignore on read.
N/A
12
Enable PortN
Late Event
R/W
A
‘
0
’
does not allow out-of-window collisions to increment portN
’
s Late Event
Counter. A
‘
1
’
does allow it.
0
11
Auto-Clear
R/W
A
‘
0
’
causes Interrupt Status Register and Search Port Match Register to
automatically clear when read.
A
‘
1
’
requires that the appropriate register bits be written to be cleared. This is
done by writing a
‘
1
’
to the bit(s) that are to be cleared.
0
10
Statistics
Enable
R/W
Turns statistics gathering on and off.
A
‘
1
’
enables statistics gathering.
‘
0
’
disables statistics gathering.
1
9
Send /T/R
R/W
Forces a good /T/R after each 100 Mbps transmission.
A
‘
1
’
forces /T/R.
‘
0
’
disables forced /T/R.
0
8
Isolate 100
R/W
Isolates the IR100CFS stack signal and provides an output pin for disabling an
external backplane transceiver.
A
‘
1
’
isolates.
‘
0
’
does not isolate.
0
7
Isolate 10
R/W
Isolates the IR10COL and IR10CFS signals and provides an output pin for
disabling an external backplane transceiver.
A
‘
1
’
isolates.
‘
0
’
does not isolate.
0
6
CountMode
R/W
Changes the definition of portReadableFrames to only count Unicast Frames.
A
‘
1
’
counts Unicast only.
‘
0
’
counts all.
0
5
Arbitration Input
Value
R
As read from input pin.
N/A
4
Zero Counters
R/W
A
‘
1
’
causes the LXT980 to sequentially walk through each counter location
and zero its contents
2
. When all counter locations have been cleared
3
, this bit
will be reset to a
‘
0
’
.
0
3
Enable FIFO
error
R/W
When set to
‘
1
’
, the LXT980 enters transmit collision upon detection of a data
rate mismatch.
1
2
Enable
Manchester
Code Violation
R/W
When set to
‘
1
’
, the LXT980 enters transmit collision upon detection of a
Manchester code violation (10 Mbps only)
0
1:0
Reserved
R/W
Reserved - Write as
‘
0s; ignore on read.
N/A
1. R = Read only; R/W = Read/Write.
2. While zeroing is in progress, the CPU will be locked out from accessing the statistics RAM until the Zero Counters bit has
been reset back to
‘
0
’
. This will be approximately 15
μ
s.
3. The rptrMonitorPortBroadcastPkts and rptrMonitorPortMulticastPkts counters (refer to
Table 51 on page 80
) are not cleared
by the Zero Counters bit.
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