參數(shù)資料
型號(hào)： LXT9784BC
英文描述： LAN TRANSCEIVER|OCTAL|BGA|324PIN|PLASTIC
中文描述： 網(wǎng)絡(luò)收發(fā)器|八路|的BGA | 324PIN |塑料
文件頁(yè)數(shù)： 37/68頁(yè)
文件大?。?/td> 1177K
代理商： LXT9784BC
Low-Power Octal PHY
—
LXT9784
Datasheet
37
10BASE-T SMII Data Reception
SMII data is signaled in ten-bit segments. Each segment is delimited by a SYNC pulse (every 10
clocks). In 10BASE-T mode, the data rate is one-tenth the 100 Mbps rate, therefore each segment
is repeated ten times so that every 10 segments represent a new byte of data.
2.4.1.2
10BASE-T Receive Buffer and Filter
In 10 Mbps mode, data is received on TPIP
n
and TPIN
n
, after passing through isolation
transformers. The filters implemented inside each LXT9784 PHY for 10BASE-T operation are
tuned for supporting a single magnetics that are shared with the 100BASE-TX side. The receive
buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the
requirements of the 10BASE-T standard. The filters are responsible for noise immunity, data
acceptance and rejection conditions.
The filter rejects the differential pulses listed next. These rejectable single-cycle sine waves are
discarded only if they are preceded by 4-bit times (400 ns) of silence. All other activity is
determined to be either data, link test pulses, auto-negotiation fast link pulses, or the idle condition
of peak magnitude less than 300 mV.
Differential pulses with a peak magnitude of less than 300 mV.
Continuous sinusoids with a differential amplitude less than 6.2 V peak to peak and frequency
less than 2 MHz.
Sine waves of a single cycle duration, starting with phase 0 or 180, that have a differential
amplitude less than 6.2 V peak to peak and a frequency of at least 2 MHz and not more than 16
MHz.
2.4.1.3
10BASE-T Error Detection and Reporting
In 10BASE-T mode, the LXT9784 can detect errors in the receive data. As error is defined only in
cases that TP-IDLE is not detected at the end of the frame (200 ns without mid-bit transitions).
2.4.1.4
10BASE-T Link Integrity
The link integrity in 10 Mbps works with link pulses. Each LXT9784 PHY senses and
differentiates those link pulses from fast link pulses and from 100BASE-TX idles. For link pulse
and for 100BASE-TX idles, the PHY uses parallel detection of the respective technology.
For fast link pulses, the PHY uses auto-negotiation. The 10BASE-T link pulses or NLPs are driven
on the TPO
n
line. The link beat pulse is also used to determine if the receive pair polarity is
reversed. If reversed the polarity is corrected internally.
2.4.1.5
10BASE-T Jabber Control Function
Each LXT9784 PHY contains a jabber control function that when enabled, inhibits transmission
after a specified time window. The jabber timer is set to a value between 26.2 and 39 ms. When the
PHY detects continuous transmission for longer than this time, it prevents further transmissions
from going out in the wire until it detects that the MAC TXEN
n
signal (in RMII mode) or the
TX_EN signal (in SMII mode) has been inactive for at least 314 ms.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT9784BE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|OCTAL|BGA|324PIN|PLASTIC
LXT9785 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers
LXT9785BC 制造商:Intel 功能描述:DATACOM, ETHERNET TRANSCEIVER, PBGA241
LXT9785BC.D0 制造商:Cortina Systems Inc 功能描述:DATACOM, INTERFACE CIRCUIT, PBGA241
LXT9785HC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|OCTAL|QFP|208PIN|PLASTIC
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