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參數(shù)資料
| 型號： | LXT9782HC |
| 英文描述： | LAN TRANSCEIVER|OCTAL|QFP|208PIN|PLASTIC |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器|八路| QFP封裝| 208PIN |塑料 |
| 文件頁數(shù)： | 42/68頁 |
| 文件大?。?/td> | 1177K |
| 代理商： | LXT9782HC |
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LXT9784
—
Low-Power Octal PHY
42
Datasheet
2.9
Reset
When the LXT9784 RESET signal is asserted (active high) all internal circuits are reset. The PHY
can also be reset individually via the PHY register reset bit (register 0
’
h bit 15). Device clock
should be stable and running prior to HW RESET. Reset must be asserted for a minimum of 500
μ
s
for proper operation after de-assertion.
2.10
LED Operation
The LXT9784 has three pins per port dedicated to driving the LEDs. These drivers can indicate
link/activity, speed, and collision. The drivers also indicate that the PHY port was disabled by
management. The activity LED in this mode is triggered by both transmit and receive activities. All
three drivers are active Low.
The algorithm for computing media utilization is an average of the activity on the media over the
time of 8 maximum length packets, with minimum IPG spacing. The utilization is averaged over:
(8 packets * 1518 bytes * 8 bytes/bit * bit time) + (8 IPG * 96 bits * bit time)
The percent utilization is indicated by a specific frequency on the LED
n
_A (as shown in Table 17)
for a period of 600 ms (LED refresh rate), based on the activity of the prior 600 ms period.
In case the port is disabled, register 0.10 = 1, drivers LED
n
_A and LED
n
_B blink in unison, at a
rate of 1 Hz, 500 ms on and 500 ms off. Eliminate the indication of PHY port disable by setting the
PHY register 1B
’
h, bit 4. There is full controllability on all drivers through PHY register 1B
’
h, bits
[2:0].
The LED
n
_B state is frozen when a link is lost and is changed only after the link is re-established.
Figure 11. Simplified Interrupt Structure
Port 0 Status Changed = 1
Port Interrupt Enable from register 12
’
h
.
.
.
INT_L
Port 1 Status Changed = 1
Port Interrupt Enable from register 12
’
h
Port 7 Status Changed = 1
Port Interrupt Enable from register 12
’
h
Phy register 12
’
h bit 0
Read
Phy register 12
’
h bit 0
Read
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT980AHC | LAN HUB CONTROLLER |
| LXT980QC | LAN HUB CONTROLLER |
| LXT9860AHC | Controller Miscellaneous - Datasheet Reference |
| LXT9860HC | Controller Miscellaneous - Datasheet Reference |
| LXT9863HC | LAN HUB CONTROLLER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT9784 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Transceiver Hardware Integrity Function Overview |
| LXT9784BC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|OCTAL|BGA|324PIN|PLASTIC |
| LXT9784BE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN TRANSCEIVER|OCTAL|BGA|324PIN|PLASTIC |
| LXT9785 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Advanced 8-Port 10/100 Mbps PHY Transceivers |
| LXT9785BC | 制造商:Intel 功能描述:DATACOM, ETHERNET TRANSCEIVER, PBGA241 |
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