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參數(shù)資料
| 型號(hào)： | LXT975QC |
| 英文描述： | LAN Transceiver |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器 |
| 文件頁數(shù)： | 25/68頁 |
| 文件大?。?/td> | 1177K |
| 代理商： | LXT975QC |
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Low-Power Octal PHY
—
LXT9784
Datasheet
25
Table 7. Miscellaneous Signal Descriptions
Ball ID
Signal Name
Type
1
Description
Y11, A11
RBIAS10_0
RBIAS10_1
B
Bias Reference Resistor 10.
A 464
1%
resistor should be connected
from this pin to ground. This determines the current source in 10M mode.
Y10, A10
RBIAS100_0
RBIAS100_1
B
Bias Reference Resistor 100.
A 619
1%
resistor should be connected
from this pin to ground. This determines the current source in 100M
mode.
K3
MCLK
I
Master Clock.
The
LXT9784 master input clock, 35/65 duty cycle,
±
50ppm.
The MCLK frequency varies, based on the mode. Mode is set by the
MODE<2:0> pins.
In RMII mode, MODE<2:0> = 001, MCLK = 50 MHz
In SMII mode, MODE<2:0> = 010, MCLK = 125 MHz
K18
RESET
I
Reset.
The Reset signal is active high and resets the LXT9784. A reset
pulse width of at least 500
μ
s should be used.
J1, K2, L2
MODE_0
MODE_1
MODE_2
I
Mode of Operation.
Sets the LXT9784 mode of operation. See Table 10.
L20, L19
ID_0
ID_1
I-PD
ID.
Sets the two most significant bits of the PHY addresses.
The ID<1:0> pins are used to set the PHY addresses for accessing the
PHY registers through the MII management interface.
B18
INT
OD
Link Status Interrupt.
The Link status change interrupt line.
K19
BP4B5B
I-PD
4B5B encoder Bypass.
If BP4B5B is high, the 4B5B encoder / 5B4B
decoder will be bypassed in 100 Mbps mode of operation.
K20
SCRMBP
I-PD
Scrambler/Descrambler Bypass.
If SCRMBP is high, the scrambler/
descrambler of TP-PMD will be bypassed in 100 Mbps mode of
operation.
K1
FRCLNK
I-PD
Force Link.
When high, force good link at speed of operation.
L3
FRC34
I-PD
Force 34 Pattern.
When high, force the 34 pattern in 100M only.
G18
MDI-X
I-PU
MDI-X Enable.
When high, enable the MDI/MDI-X automatic detection
and switch-over feature.
H19
TI
I
Test Input.
Sets the device into manufacturing test mode
(MODE<2:0>=
”
111
”
). Should be externally pulled low when not in use.
H18
TEXEC
I
Test Execute
Command.
Sets the device into async test mode
(MODE<2:0>=
”
111
”
). Should be externally pulled low when not in use.
H20
TCK
I
Test Clock.
The
test clock signal. Should be externally pulled low when
not in use.
B20
TOUT
O
Test Output.
The
test output port.
1. Refer to
Table 1 on page 11
for Signal Type Definitions.
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