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參數(shù)資料
| 型號： | LXT332 |
| 廠商： | Digital Data Communications GmbH |
| 英文描述： | 3941 |
| 中文描述： | 雙T1/E1線路接口單元與水晶無衰減 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大?。?/td> | 777K |
| 代理商： | LXT332 |
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Transmit Tip and Ring - Port 0.
The tip and ring pins for each port are dif-
ferential driver outputs designed to drive a 35 - 200
load. Line matching
resistors and transformers can be selected to give the desired pulse height.
See Figures 19 through 21.
Ground.
Ground return for power supply TVCC0.
+ 5 volt power supply input for the port 0 transmit driver.
TVCC0 must
not vary from TVCC1 or VCC by more than ± 0.3 V.
Driver Fail Monitor.
This signal goes High to indicate a driver output short
in one or both ports.
Port Select - Port 0.
This input accesses the serial interface registers for
port 0. For each read or write operation, PS must transition from High to
Low, and remain Low.
Pattern Detect - Port 0.
Unless the QRSS function is selected by the VCQE
pin, PD0 functions as an AIS alarm indicator. The AIS pattern is detected by
the receiver, independent of any loopback mode. AIS goes High when less
than three zeros have been detected in any string of 2048 bits. AIS returns
Low when the received signal contains more than three zeros in 2048 bits.
(LOS is available via the SIO register and interrupt.)
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If the QRSS function is enabled by the VCQE pin, PD0 remains High until
pattern sync is reached with the received signal. Once pattern lock is
obtained, PD0 goes Low. (The sync/out-of-sync criteria is less than 3/4
errors in 128 bits.) After sync acquisition, bit errors cause PD0 to go High
for half a clock cycle. This output can be used to trigger an external error
counter.
Receive Tip and Ring - Port 0.
RTIP and RRING comprise the receive line
interface. This input pair should be connected to the line through a center-
tapped 1:2 transformer.
Clock Edge Select.
When CLKE is High, RPOS/RNEG or RDATA out-
puts are valid on the falling edge of RCLK, and SDO is valid on the rising
edge of SCLK. When CLKE is Low, RPOS/RNEG or RDATA outputs are
valid on the rising edge of RCLK, and SDO is valid on the falling edge of
SCLK.
Receive Tip and Ring - Port 1.
RTIP and RRING comprise the receive line
interface. This input pair should be connected to the line through a center-
tapped 1:2 transformer.
Pattern Detect - Port 1.
Reports AIS and QRSS pattern reception. See
PD0 signal description for details.
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Port Select - Port 1.
This input accesses the serial interface registers for
port 1. For each read or write operation, PS must transition from High to
Low, and remain Low.
Transmit Tip and Ring - Port 1.
The tip and ring pins for each port are dif-
ferential driver outputs designed to drive a 35 - 200
load. Line matching
resistors and transformers can be selected to give the desired pulse height.
See Figures 13 through 15.
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