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參數(shù)資料
| 型號： | LXT331PE |
| 英文描述： | LINE INTERFACE|CMOS|LDCC|44PIN|PLASTIC |
| 中文描述： | 線路接口|的CMOS | LDCC | 44PIN |塑料 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大?。?/td> | 395K |
| 代理商： | LXT331PE |
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LXT331
—
Dual T1/E1 Line Interface Unit
12
Datasheet
2. Pulse width: the monitor distinguishes between marks and noise pulses by the pulse width.
LXT331 requires a mark pulse to be at least 120 ns wide (typical).
As shown in
Figure 4 on page 13
, there are two type of marks:
“
A
”
and
“
B
”
. C1 and C2 detect
“
A
”
marks while the AND gate (A1) ensures that both mark signals are present at the same time. If the
pulse widths are adequate, i.e. both a positive mark on MTIP and a negative mark on MRING, the
A1 output goes High. Likewise C3 and C4 detect
“
B
”
marks. If the pulse meets the minimum width
requirement, the AND gate (A2) output goes High when there are both a negative mark on MTIP
and a positive mark on MRING. The OR gate (O1) passes the mark, as the signal
“
zero
”
, on to the
clock/counter circuit which controls the DPM output.
A latch samples the counter and goes High if the DPM circuit sees 63 consecutive zeros. Any mark
resets the counter. The DPM signal goes High after the 63
rd
zero.
2.2.3
Driver Failure Monitor
The transceiver incorporates an internal Driver Failure Monitor (DFM) that observes TTIP and
TRING. Driver failure is detected with a capacitor that is charged as a function of driver output
current, and discharged as a measure of the maximum allowable current. Shorted lines draw excess
current, overcharging the cap. When the capacitor charge deviates outside the nominal charge
window, a driver failure is reported. In Host mode the DFM bit is set in the serial word. In both
Hardware and Host modes the DFM pin goes High. During a long string of spaces, a short-induced
overcharge eventually bleeds off, clearing the DFM flag.
2.3
Control Modes
The LXT331 transceiver operates in either standalone Hardware mode (default) or Host mode. In
Host mode a microprocessor controls the LXT331 via the serial I/O port (SIO) which provides
common access to both LIUs. In Hardware mode, the transceiver is controlled through individual
pins; a microprocessor is not required.
Table 2. Equalizer Control Inputs - Hardware Mode
1
LEN2
LEN1
LEN0
Line Length
2
Cable Loss
3
Application
Frequency
Low
High
High
High
High
High
Low
Low
High
High
High
Low
High
Low
High
0 - 133 ft ABAM
133-266 ft ABAM
266-399 ft ABAM
399-533 ft ABAM
533-655 ft ABAM
0.6 dB
1.2 dB
1.8 dB
2.4 dB
3.0 dB
DSX-1
1.544 MHz
Low
Low
Low
Low
Low
High
ITU Recommendation G.703
E1 - Coax (75
)
E1 - Twisted-pair (120
)
2.048 MHz
Low
High
Low
FCC Part 68, Option A
CSU
1.544 MHz
1. LEN0-2 inputs are shown as High or Low for Hardware mode. For Host mode serial inputs, High = 1 and
Low = 0.
2. Line length from LXT331 to DSX-1 cross-connect point.
3. Maximum cable loss at 772 kHz.
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相關代理商/技術參數(shù) |
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| LXT331PH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE INTERFACE|CMOS|LDCC|44PIN|PLASTIC |
| LXT331QE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE INTERFACE|CMOS|QFP|44PIN|PLASTIC |
| LXT331QH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LINE INTERFACE|CMOS|QFP|44PIN|PLASTIC |
| LXT332 | 制造商:LVL1 制造商全稱:LVL1 功能描述:Dual T1/E1 Line Interface Unit with Crystal-less Attenuation |
| LXT332PE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Line Interface |
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