參數(shù)資料
型號(hào): LXT318NE
英文描述: PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|DIP|28PIN|PLASTIC
中文描述: 的PCM收發(fā)器|單|優(yōu)稅PCM-30/E-1 |的CMOS |雙酯| 28腳|塑料
文件頁(yè)數(shù): 23/26頁(yè)
文件大?。?/td> 402K
代理商: LXT318NE
T1 CSU/ISDN PRI Transceiver
LXT310
Datasheet
23
Table 13. LXT310 Master Clock and Transmit Timing Characteristics
(See
Figure 11
)
Parameter
Sym
Min
Typ
1
Max
Units
Notes
Master clock frequency
MCLK
1.544
MHz
Master clock tolerance
MCLKt
±100
ppm
Master clock duty cycle
MCLKd
40
60
%
Crystal frequency
fc
6.176
MHz
LXT310 only
Transmit clock frequency
TCLK
1.544
MHz
Transmit clock tolerance
TCLKt
±100
ppm
Transmit clock duty cycle
TCLKd
10
90
%
TPOS/TNEG to TCLK setup time
t
SUT
50
ns
TCLK to TPOS/TNEG hold time
t
HT
50
ns
1. Typical values are at 25
°
C and are for design aid only; they are not guaranteed and not subject to production testing.
Figure 11. LXT310 Transmit Clock Timing Diagram
Table 14. LXT310 Serial I/O Timing Characteristics
(See
Figure 12
and
Figure 13
)
Parameter
Sym
Min
Typ
1
Max
Units
Test Conditions
Rise/Fall time - any digital output
t
RF
100
ns
Load 1.6 mA, 50 pF
SDI to SCLK setup time
t
DC
50
ns
SCLK to SDI hold time
t
CDH
50
ns
SCLK low time
t
CL
240
ns
SCLK high time
t
CH
240
ns
SCLK rise and fall time
t
R
, t
F
50
ns
CS
to SCLK setup time
t
CC
50
ns
SCLK to
CS
hold time
t
CCH
50
ns
CS
inactive time
t
CWH
250
ns
SCLK to SDO valid
t
CDV
200
ns
SCLK falling edge or
CS
rising edge
to SDO high Z
t
CDZ
100
ns
1. Typical values are at 25
°
C and are for design aid only; they are not guaranteed and not subject to production testing.
t
HT
t
SUT
TCLK
TPOS
TNEG
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