參數(shù)資料
型號: LXT310JE
英文描述: PCM Transceiver
中文描述: 收發(fā)器的PCM
文件頁數(shù): 18/26頁
文件大小: 402K
代理商: LXT310JE
LXT310
T1 CSU/ISDN PRI Transceiver
18
Datasheet
3.2
LXT310 Hardware Mode Applications
Figure 8
is a typical 1.544 Mbps ISDN PRI application with the LXT310, a T1/ESF framer and an
LXP600A clock adapter. The LXT310 is operating in the Hardware mode with B8ZS encoding
enabled (MODE pin 5 tied to RCLK). As in the T1/CSU application,
Figure 7
, this configuration is
illustrated with a single power supply bus. CMOS control logic is used to set both LBO pins high,
Figure 7. Typical LXT310 Host Mode T1/CSU Application
FSYNC
TCLK
TPOS
TNEG
SPS
RNEG
RPOS
RCLK
T1/ESF
FRAMER
MCLK
TCLK
TPOS
TNEG
MODE
RNEG
RPOS
RCLK
XTALIN
XTALOUT
JASEL
LOS
TTIP
TGND
CLKE
SCLK
CS
SDO
SDI
INT
RGND
RV+
RRING
RTIP
LATN
EGL
TRING
TV+
LXT310
TRANSCEIVER
LXP600A CLAD
CLKI
CLKO
1.544
MHz
2.048 MHz
6.176
MHz
1.0
μ
F
V+
100
0.1
μ
F
1:1
1.544 MHz
T1 Line
Transmit
T1 Line
Receive
1:2
0V
V+
12.5
12.5
68
μ
F
TMSYNC
CS
SDO
SDI
INT
SCLK
To Host Controller
V+
NOTE:
The LXT310 is compatible
with a wide variety of framing/
signaling devices
See Note 1
1.544
MHz
22 k
See
Figure 3
&
Figure 6
FSI
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