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參數(shù)資料
| 型號： | LXT310 |
| 廠商： | Digital Data Communications GmbH |
| 英文描述： | T1 CSU/ISDN PRI Transceiver |
| 中文描述： | T1的CSU /綜合業(yè)務(wù)數(shù)字網(wǎng)革命制度黨收發(fā)器 |
| 文件頁數(shù)： | 5/18頁 |
| 文件大?。?/td> | 365K |
| 代理商： | LXT310 |
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The figure on the front page of this section is a block dia-
gram of the LXT310. The transceiver may be controlled by
a microprocessor through the serial port (Host Mode), or by
individual pin settings (Hardware Mode). The jitter atten-
uator may be positioned in either the transmit or receive
path.
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The LXT310 is a low-power CMOS device. It operates
from a single +5 V power supply which can be connected
externally to both the transmitter and receiver. However,
the two inputs must be within ± .3 V of each other, and
decoupled to their respective grounds separately. Refer to
Application Information for typical decoupling circuitry.
Isolation between the transmit and receive circuits is pro-
vided internally.
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The twisted-pair input is received via a 1:1 transformer.
Recovered data is output at RPOS/RNEG (RDATA in un-
ipolar mode), and the recovered clock is output at RCLK.
Refer to Test Specifications for receiver timing.
The signal received at RPOS and RNEG is processed
through the receive equalizer. The Equalizer Gain Limit
(EGL) input determines the maximum gain that may be ap-
plied at the equalizer. When set Low, up to 36 dB of gain
may be applied.
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