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3.Circuit attenuates jitter at 20 dB/decade above the corner frequency.
4.In accordance with ITU G.703/ETS 300166 return loss specifications when wired per Figure 7 (E1).
5.Guaranteed by design.
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Power dissipation while driving 75
load over operating temperature range. Includes device and load. Digital input lev-
els are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load.
2.Functionality of pins 23 and 25 depends on mode. See Host/Hardware Mode descriptions.
3.Output drivers will output CMOS logic levels into CMOS loads.
4.Except MTIP and MRING ILL = ± 50 μA.