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參數(shù)資料
| 型號： | LXD975A |
| 英文描述： | LXD975A - LXD975A Demo Board for 10/100 Applications |
| 中文描述： | LXD975A - LXD975A演示板的10/100應(yīng)用 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 243K |
| 代理商： | LXD975A |
Demo Board for 10/100 and 100BASE-FX Applications
—
LXD970A
Development Kit Manual
11
4.0
Hardware Control Interface
4.1
Multi-Function Pins
The Hardware Control Interface (JP1) provides access to the Multi-Function (MF) pins which
decode 4-level supply voltages to establish two independent settings per pin. The first setting
determines chip address. The second setting determines configuration of the LXD970A. The 4-
level inputs referred to as V
MF
1, V
MF
2, V
MF
3 and V
MF
4 are shown in Table 3.
To select an Input Level place a jumper on the appropriate pins. The 4-level input pins (V
MF
1,
V
MF
2, V
MF
3 and V
MF
4) are identical for each Multi-Function (MF) section. See Figure 3 for
jumper placement.
Table 3. MF Pins Input Voltage Levels
Parameter
Symbol
Min
Max
Units
Input Voltage Level 1
V
MF
1
Vcc - 0.5
-
V
Input Voltage Level 2
V
MF
2
(Vcc/2) + 0.5
Vcc - 1.2
V
Input Voltage Level 3
V
MF
3
1.2
Vcc/2 - 0.5
V
Input Voltage Level 4
V
MF
4
-
0.5
V
Figure 4. Hardware Control Interface Jumper Placement
NOTES:
1. TRSTE and MDDIS functions are not labeled on the board.
2. CFG1, CFG0 and FDE are pin names for the manual pins and are not labeled on the board.
MDS
1
MMMN TSE
2
2
2
1
pin 49
pin 50
pin 1
pin 2
MF0
MF1
MF2
MF3
MF4
V
M
1
V
M
2
V
M
3
V
M
4
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