
Microsemi
Linfinity Microelectronics Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
Copyright
2000
Rev. 2.0, 2005-11-02
W
M
.
C
LX8386x-xx
1.5A Low Dropout Positive Regulators
P
RODUCTION
D
ATA
S
HEET
TM
A B S O L U T E M A X I M U M R A T I N G S
Power Dissipation...................................................................................Internally Limited
Input Voltage................................................................................................................10V
Input to Output Voltage Differential.............................................................................10V
Maximum Output Current............................................................................................1.5A
Operating Junction Temperature
Plastic (DT, DD, P Packages)................................................................................150°C
Storage Temperature Range....................................................................... -65°C to 150 °C
Peak Package Solder Reflow Temp (40 seconds max. exposure).................260°C (+0, -5)
Note:
Exceeding these ratings could cause damage to the device. All voltages are with respect to
Ground. Currents are positive into, negative out of specified terminal.
T H E R M A L D A T A
DD
Plastic TO-263 3-Pin
THERMAL RESISTANCE
-
JUNCTION TO
A
MBIENT
,
θ
JA
THERMAL RESISTANCE
-
JUNCTION TO
T
AB
,
θ
JT
P
Plastic TO-220 3-Pin
THERMAL RESISTANCE
-
JUNCTION TO
A
MBIENT
,
θ
JA
THERMAL RESISTANCE
-
JUNCTION TO
T
AB
,
θ
JT
DT
Plastic TO-252 3-Pin
THERMAL RESISTANCE
-
JUNCTION TO
A
MBIENT
,
θ
JA
THERMAL RESISTANCE
-
JUNCTION TO
T
AB
,
θ
JT
60
°
C/W
2.7°C/W
60
°
C/W
2.7°C/W
60
°
C/W
2.7°C/W
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x
θ
JT
).
The
θ
JA
&
θ
JT
numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
P A C K A G E P I N O U T
1
V
IN
V
OUT
ADJ /
GND*
2
3
TAB is V
OUT
DD
P
ACKAGE
(3-
PIN
)
(Top View)
TAB is V
OUT
V
IN
V
OUT
ADJ/
GND
*
3
2
1
DT
P
ACKAGE
(3-
PIN
)
(Top View)
TAB is V
OUT
ADJ /
GND*
V
OUT
V
IN
1
2
3
P
P
ACKAGE
(3-
PIN
)
(Top View)
RoHS Compliant 100% Matte Tin Lead Finish
*
Pin 1 is GND for fixed voltage versions
B L O C K D I A G R A M
Thermal
Limit Circuit
Bias Circuit
Bandgap
Circuit
Control
Circuit
Output
Circuit
SOA
Protection
Circuit
Current
Limit Circuit
V
IN
ADJ or
GND*
V
OUT
*
Pin 1 is GND for fixed voltage versions
P
A
C
K
A
G
E
D
A
T
A