參數(shù)資料
型號(hào): LX8385A-33CDL
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: THREE-TERMINAL POSITIVE FIXED VOLTAGE REGULATORS
中文描述: 三端固定電壓調(diào)節(jié)器
文件頁(yè)數(shù): 2/11頁(yè)
文件大?。?/td> 143K
代理商: LX8385A-33CDL
Microsemi
Linfinity Microelectronics Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 2
Copyright
2000
Rev. 2.1d, 2001-03-15
W
M
.
LX8384x-xx
5A Low Dropout Positive Regulators
P
RODUCTION
A M I C R O S E M I C O M P A N Y
Power Dissipation....................................................................................Internally Limited
Input Voltage.................................................................................................................10V
Input to Output Voltage Differential..............................................................................10V
Operating Junction Temperature
Plastic (DT, DD, P Packages)................................................................................150°C
Storage Temperature Range .......................................................................-65°C to 150 °C
Lead Temperature (Soldering, 10 Seconds)...............................................................300°C
Note 1:
Exceeding these ratings could cause damage to the device. All voltages are with respect to
Ground. Currents are positive into, negative out of specified terminal.
DD
Plastic TO-263 3-Pin
THERMAL RESISTANCE
-
JUNCTION TO
A
MBIENT
,
θ
JA
THERMAL RESISTANCE
-
JUNCTION TO
T
AB
,
θ
JT
P
Plastic TO-220 3-Pin
THERMAL RESISTANCE
-
JUNCTION TO
A
MBIENT
,
θ
JA
THERMAL RESISTANCE
-
JUNCTION TO
T
AB
,
θ
JT
DT
Plastic TO-252 3-Pin
THERMAL RESISTANCE
-
JUNCTION TO
A
MBIENT
,
θ
JA
THERMAL RESISTANCE
-
JUNCTION TO
T
AB
,
θ
JT
60
°
C/W
2.7°C/W
60
°
C/W
2.7°C/W
60
°
C/W
2.7°C/W
Junction Temperature Calculation: T
J
= T
A
+ (P
D
x
θ
JT
).
The
θ
JA
&
θ
JT
numbers are guidelines for the thermal performance of the device/pc-board
system. All of the above assume no ambient airflow.
1
V
IN
ADJ /
GND*
V
OUT
2
3
TAB is V
OUT
DD P
ACKAGE
(3-
PIN
)
(Top View)
V
IN
V
OUT
ADJ/
GND*
TAB is V
OUT
3
2
1
DT P
ACKAGE
(3-
PIN
)
(Top View)
TAB is V
OUT
ADJ /
GND*
V
OUT
V
IN
1
2
3
P
P
ACKAGE
(3-
PIN
)
(Top View)
*
Pin 1 is GND for fixed voltage versions
Thermal
Limit Circuit
Bias Circuit
Bandgap
Circuit
Control
Circuit
Output
Circuit
SOA
Protection
Circuit
Current
Limit Circuit
V
IN
ADJ or
GND*
V
OUT
*
Pin 1 is GND for fixed voltage versions
P
A
C
K
A
G
E
D
A
T
A
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