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參數(shù)資料
| 型號(hào)： | LX64V-5FN100C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SWITCH DIGITAL 100FPBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 01/Aug/2011 |
| 標(biāo)準(zhǔn)包裝： | 176 |
| 功能： | 開(kāi)關(guān) |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 100-LBGA |
| 供應(yīng)商設(shè)備封裝： | 100-FPBGA（11x11） |
| 包裝： | 托盤(pán) |
Lattice Semiconductor
ispGDX2 Family Data Sheet
2
Figure 1. ispGDX2 Block Diagram (256-I/O Device)
Introduction
The ispGDX2 family is Lattice’s second generation in-system programmable generic digital crosspoint switch for
high speed bus switching and interface applications.
The ispGDX2 family is available in two options. The standard device supports sysHSI capability for ultra fast serial
communications while the lower-cost “E-series” supports the same high-performance FPGA fabric without the
sysHSI Block.
This family of switches combines a exible switching architecture with advanced sysIO interfaces including high
performance sysHSI Blocks, and sysCLOCK PLLs to meet the needs of the today’s high-speed systems. Through
a muliplexer-intensive architecture, the ispGDX2 facilitates a variety of common switching functions.
The availability of on-chip control logic further enhances the power of these devices. A high-performance solution,
the family supports bandwidth up to 38Gbps.
Every device in the family has a number of PLLs to provide the system designer with the ability to generate multiple
clocks and manage clock skews in their systems.
GDX Block
sysCLOCK
PLL
sysCLOCK
PLL
SERDES
sysIO Bank
SERDES
GDX Block
SERDES
GDX Block
SERDES
GDX Block
FIFO
ISP & Boundary Scan
Test Port
GDX
Bloc
k
SERDES
sysIO
Bank
sysIO
Bank
SERDES
GDX
Bloc
k
SERDES
GDX
Bloc
k
SERDES
GDX
Bloc
k
FIFO
sysIO
Bank
sysIO
Bank
SERDES
GDX
Bloc
k
GDX
Bloc
k
GDX
Bloc
k
GDX
Bloc
k
FIFO
sysHSI
Block
sysHSI
Block
sysHSI
Block
sysHSI
Block
sysHSI
Bloc
k
sysHSI
Bloc
k
sysHSI
Bloc
k
sysHSI
Bloc
k
sysCLOCK
PLL
sysCLOCK
PLL
Global Routing Pool
(GRP)
SELECT
DEVICES
DISCONTINUED
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