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參數(shù)資料
| 型號： | LX1800ILD-TR |
| 廠商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, DSO8 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLP-8 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 167K |
| 代理商： | LX1800ILD-TR |
LX1800
PRODUCTION DATA SHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 4
Copyright
2004
Rev. 1.0, 2006-01-05
WWW
.Microse
m
i
.CO
M
SMBus to Analog Interface
TM
SMBUS COMMUNICATION FORMAT
The LX1800 looks for its unique address each time it
detects a “start condition”. If the address does not match,
the LX1800 ignores all bus activity until it encounters
another “start condition”. If the address is a match, the
LX1800 acknowledges that it has detected its address and a
W/R bit to either read or write data. If the W/R bit is a “0”,
signifying a “write command”, the next byte of data sent
from the host will be the index. The index points to an
internal register in the LX1800 that will be the object of the
subsequent data transfers. There are four internal registers
within the LX1800: The Control register, the DAC register
,the ADC register, and the MISC register. In a write
command, the LX1800 will acknowledge the receipt of a
valid index. After the index, there may be another byte of
data; if so, this byte of data is loaded into the indexed
register. The LX1800 will acknowledge receipt of the data
byte. If the write command does not contain data, the
command line will be terminated by a “stop condition”
received from the host. If for some reason, the data transfer
is corrupted prior to acknowledgement, the LX1800 will
not acknowledge receipt of the byte in question and will not
take action on the incomplete data. The LX1800 can receive
only one data byte in a write command and will ignore all
additional bus activity once it has acknowledged receipt of
the data byte until the next “start condition” is detected.
Receipt of a “stop condition” or “start condition” will reset
the address detection state machine. The LX1800 does not
support “Packet Error Code”.
The host can read the contents of the indexed register
within the LX1800 using a read command line. In this
command line the W/R bit is set to “1”. Upon receipt of a
read command, the LX1800 will acknowledge that it has
detected its address and a valid W/R bit; then it will put a
copy of the one byte of data from the indexed register onto
the bus. (As explained above, the index may be changed
using a write command with or without an additional data
byte.) Once the LX1800 has placed the byte of data on the
serial bus, it will ignore all additional bus activity until the
next “start condition” is detected.
Write Format (Two optional packet lengths)
Start
Address
W/R
Ack
Data
Ack
Stop
0101100b or
0101101b
0
Index
Start
Address
W/R Ack Data
Ack
Data
Ack
Stop
0101100b or
0101101b
0
Index
1 byte
Data
Read Command Format:
Start
Address
W/R
Ack
Data
Ack
Stop
0101100b or
0101101b
1
Read Indexed
Register
Repeated Start Command Format:
The LX1800 will support the execution of successive
commands that are not separated by “stop conditions”
provided the commands are otherwise formatted as
indicated above.
GENERAL SMBUS PROTOCOL SUMMARY
(see SMBus specification version 2.0 for more details).
Start condition: Host sends a high-to-low SDA transition
while SCL is high.
Address: Host sends to 0101100 ADR=GND; 0101101
ADR = VCC
W/R: Host sends a “Lo” bit for an instruction with a
DATA Write and a “Hi” bit for a DATA Read.
Acknowledge: LX1800 and Host let SDA go high while
SCL is low after data byte transfer indicating next byte
may be sent.
Stop Condition: A low-to-high SDA transition while
SCL is high.
Normal condition: SDA transitions only while SCL is
low.
For timing information see SMBus specification version
2.0.
Data is transferred with the MSB first.
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