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參數(shù)資料
| 型號： | LX1745-CPW |
| 廠商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | Triple Output Boost ? LED Driver / LCD Bias |
| 中文描述： | LED DISPLAY DRIVER, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 439K |
| 代理商： | LX1745-CPW |
LX1745
P
RODUCTION
D
ATASHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 10
W
M
.
C
Triple Output Boost – LED Driver / LCD Bias
I N T E G R A T E D P R O D U C T S
Copyright
2000
Rev. 1.1a, 2004-02-06
APPLICATION NOTE
N
EGATIVE
LCD
B
IAS
G
ENERATION
For applications that require it, a negative bias can be
easily generated using an inductorless charge pump
consisting of only four additional discrete components
(Figure 8).
LX1745
V
BAT
= 1.6V to 6.0V
SWx
V
OUT
R
1
R
2
FBx
- V
OUT
D
3
D
4
Figure 8 –
Negative Bias Generation
This negative output is a mirror of the positive output
voltage. However, it is unregulated.
If a regulated negative bias is desired then this is also
possible with some additional components. A low current
shunt regulator (LX6431 or LX432) and a bipolor pass
element can form a simple negative voltage LDO (Figure
9).
LX1745
V
BAT
= 1.6V to 6.0V
SWx
V
OUT
R
1
R
2
FBx
D
3
D
4
V
NEG_LCD
LX6431,
LX432
R
3
R
4
R
5
Figure 9 –
Regulated Negative Bias
R
3
is sized to meet the minimum shunt current required for
regulation while R
4
and R
5
are calculated. If R
5
is selected
to be 100k
then R
4
is calculated using the following
equation:
=
REF
LCD
_
NEG
V
V
+
5
4
R
R
1
eq. 13
where V
REF
is a -2.5V in the case of the LX6431.
F
EED
-F
ORWARD
C
APACITANCE
Improved efficiency and ripple performance can be
achieved by placing a feed-forward capacitor across the
feedback resistor connected to the output (Figure 2). A
recommended value of 1nF should be used.
PCB
L
AYOUT
Minimizing trace lengths from the IC to the inductor,
diode, input and output capacitors, and feedback
connection (i.e. pin 3) are typical considerations.
Moreover, the designer should maximize the DC input and
output trace widths to accommodate peak current levels
associated with this circuit.
SHDN
SHDN2
SHDN1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
0
Table 1
–
Enable Logic
LCD1
1
1
1
0
0
0
0
LCD2
0
1
0
1
0
0
0
0
LED
0
0
1
1
0
0
0
0
A
P
P
L
I
C
A
T
I
O
N
S
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