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參數(shù)資料
| 型號： | LX1711CDB |
| 廠商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | EVALUATION KIT |
| 中文描述： | 54 W, 1 CHANNEL, AUDIO AMPLIFIER, PDSO28 |
| 封裝： | PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大小： | 339K |
| 代理商： | LX1711CDB |
LXE1710 E
VALUATION
B
OARD
U
SER
G
UIDE
Microsemi
Linfinity Microelectronics Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 14
Copyright
2000
Rev. 1.1, 2000-12-01
G
ATE
R
ESISTOR
Series resistors (R6, R10, R11, R12) can be added to
the gate of MOSFETs (Q1 to Q4) to control the
switching transition times. This reduces signal
distortion as seen in the THD+N vs. Output Power
graph below. The slower switching speeds will
however, increase power dissipation and therefore
slightly decrease the overall efficiency of the amplifier.
P+
N+
OUT+
V
IN
Q1
Q2
R12
10
R11
10
- 3451
resistors, which improves (decreases) the THD+N
from 0.1% to 0.05% with a slight impact on efficiency
of approximately 2%. The recommended gate resistor
1 6!
O
SCILLATOR
C
ONFIGURATION
.
1 $
The oscillator is programmed by the external timing
components RPWM and CPWM. For a nominal
frequency of 333kHz, RPWM and CPWM should be
set to 49.9kOhms and 100pF respectively. Note that
in order to keep the slope of the PWM ramp voltage
proportional to the supply voltage, both the ramp peak
and valley voltages, and the charge and discharge
currents are proportional to the supply voltage. This
keeps the frequency relatively constant while keeping
the slope of the PWM ramp proportional to the voltage
on the VDD pin. For operating frequencies other than
333kHz, the frequency can be approximated by the
following equation:
ns
C
R
PWM
PWM
320
)
)(
)(
577
.
1
Frequency
+
=
M
ULTI
C
HANNEL
R
EQUIREMENTS AND
F
REQUENCY
S
YNCHRONIZATION
For applications that require more than a single
channel, the oscillators of multiple LX1710/1711
controllers can be configured for synchronous
operation. One unit, the master, is programmed for
the desired frequency with the RPWM and CPWM as
usual. Additional units will be slave units, and their
oscillators will be disabled by leaving the RPWM pin
disconnected. The CLOCK pin and the CPWM pin of
the slave units should be tied to the CLOCK pin and
the CPWM pin of the master unit respectively. In this
configuration, the CLOCK pins of the slave units begin
receiving instead of transmitting clock pulses. Also,
the CPWM pins quit driving the PWM capacitor in the
slave units. Note that for optimum performance, all
slave units should be located within a few inches of the
master unit.
Gate Resistor Impact On THD+N
0.001
100
20
0.005
0.01
0.1
1
2
10
50
0.26978
0.04675
T
50m
30
100m
200m
500m
1
2
5
10
20
24.56
1.131
Output Power (W)
f
IN
= 1kHz
No Gate Resistor
With 10
Gate Resistor
V
IN
= 15V
R
L
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