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參數資料
| 型號： | LX1688CPW |
| 廠商： | MICROSEMI CORP-ANALOG MIXED SIGNAL GROUP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | MULTIPLE LAMP CCFL CONTROLLER |
| 中文描述： | FLUORESCENT LIGHT CONTROLLER, 70 kHz SWITCHING FREQ-MAX, PDSO24 |
| 封裝： | ROHS COMPLIANT, PLASTIC, TSSOP-24 |
| 文件頁數： | 7/15頁 |
| 文件大?。?/td> | 624K |
| 代理商： | LX1688CPW |
Microsemi
Integrated Products, Power Management
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 7
Copyright
2001
Rev. 1.1a, 2003-03-21
W
M
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C
RangeMAX
LX1688
M
ULTIPLE
L
AMP
CCFL
C
ONTROLLER
I N T E G R A T E D P R O D U C T S
D E T A I L E D D E S C R I P T I O N
The LX1688 is a backlight controller specifically
designed with a special feature set needed in multiple
lamp desktop monitors, and other multiple lamp displays.
While utilizing the same architecture as Linfinity’s
LX1686 controller it eliminates the synchronized digital
dimming and adds, lamp ‘strike’ count out timer, lamp
fault status output, and external clock input/output that
permits multiple controllers to synchronize their output
current both in frequency and phase.
Operation From 3.3V and/or 5.0V Input Supply
The LX1688 is designed to operate and meet all
specifications at 3.3V ±10% to 5.0V ±10%. The under
voltage lockout is set at nominally 2.8V with a 190mV
hysteresis.
Master/Slave Clock Synchronization
One or more controllers (up to 11) may be designated
as slave controllers and receive ramp reset and phase
synchronization from the designated master controller.
This will allow up to 12 lamps (24 with two lamps in
series/controller design) to all operate in phase and
frequency synchronization. This is important to prevent
random
interference
between
unpredictably changing electric and magnetic fields that
will inevitably link them.
The LX1688 has two independent oscillators, one for
lamp strike and one for the lamp run frequency. The
strike oscillator ramps the operating frequency slowly up
and down when the open lamp sense input (OLSNS)
indicates the lamp is not ignited. During this lamp strike
condition the operating frequency of each IC will vary up
and down as needed to strike its lamp. The controller is
so designed that the master controller clock remains at the
pre-selected frequency for fully ignited lamps even while
striking. Likewise the designated slave controller will not
alter the frequency or phase of the master clock during its
strike phase. Thus each controller will vary its frequency
as needed to strike its lamp then it will synchronize to the
master clock frequency and phase.
The TRI_C wave generator (see Block Diagram) sets
the rate of operating frequency variation during lamp
strike. The TRI_C generator is connected to a 6-bit
counter that times out after 63 cycles and then latches the
FAULT output high if the OLSNS input indicates no
lamp current is flowing. Even in the case of timeout fault
the master controller clock will continue to provide
synchronization to the slave controllers.
When synchronizing more than one controller the
Ramp Reset (RMP_RST), Phase Sync (PHA_SYNC),
lamps
through
and Slave Input/Output are used. RMP_RST and
PHA_SYNC should be connected between all the
controllers. The master controller should have its SLAVE
pin connected to VSS (GND) and the slave controllers
SLAVE input to VDD (High).
BEPOL Input
The BEPOL pin is a tri-mode input that controls the
polarity of the ENABLE and BRITE input signals.
Depending on the state of this pin (VDD, floating, or VSS)
the controller can be set to allow active high enable with
active high full brightness or active high or low enable with
active low full brightness (see Table 1).
BRITE Input (Dimming Input)
The BRITE input is capable of accepting either a DC
voltage (
≥
.5V to
≤
2.5V) or a PWM digital signal that is
clamped on chip (<.5V or >2.5V). A digital signal can
either be passed unfiltered to effect pulse ‘digital’ dimming
or filtered with a capacitor to effect analog dimming with a
digital PWM signal.
Analog Dimming Methods:
Mechanical or digital potentiometer set to provide 1V
to 2.5V on the wiper output. A filter cap from BRITE
to signal ground is recommended.
D/A converter output directly connected to BRITE
input. A R/C filter using a capacitor from the CPW1
input to ground for applications where the ADC
output may contain noise sufficient to modulate the
BRITE input.
A high frequency PWM digital logic pulse connected
directly to the BRITE input. The Brightness (BRT,
internal node) output will be sensitive only to the
PWM duty cycle, and not to the PWM signal
amplitude, so long as the amplitude exceeds 2.6V for
a logic high (1) and is less than .4V for a logic (0).
This pulse frequency will typically be between 1KHz
and 100KHz and will not be synchronized with the
LCD video frame rate. A capacitor (CPWM) between
CPW1 and CPW2 will integrate the PWM signal for
use by the controller.
Digital Dimming Methods:
Low frequency PWM digital logic pulses connected
directly to the BRITE input. As above the Brightness
(BRT internal) will be sensitive only to the PWM
duty cycle, and not to the PWM signal amplitude, so
long as the amplitude exceeds 2.6V for a logic high
(1) and is less than .4V for a logic (0). This pulse
frequency will typically be in the range of 90-320Hz
D
E
S
C
R
I
P
T
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N
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| LX1688CPW-TR | 制造商:Microsemi Corporation 功能描述:CCFL DRVR 5.5V 24TSSOP - Tape and Reel |
| LX1688IPW | 功能描述:IC CTRLR CCFL BACKLIGHT 24TSSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 照明，鎮(zhèn)流器控制器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:CCFL 控制器 頻率:40 ~ 80 kHz 電流 - 電源:5mA 電流 - 輸出:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) 其它名稱:90-3991V+V01 |
| LX1688IPW-TR | 制造商:Microsemi Corporation 功能描述:CCFL Controller 3.3V/5V 24-Pin TSSOP T/R 制造商:Microsemi Corporation 功能描述:CCFL DRVR 5.5V 24TSSOP - Tape and Reel |
| LX1689 | 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:Third Generation CCFL Controller |
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