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參數(shù)資料
| 型號(hào)： | LX128V-5FN208C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁(yè)數(shù)： | 4/9頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH DIGITAL 208FPBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 功能： | 開(kāi)關(guān) |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 208-BGA |
| 供應(yīng)商設(shè)備封裝： | 208-FPBGA（17x17） |
| 包裝： | 托盤(pán) |
www.latticesemi.com
1
gdx2fam_13
ispGDX2 Family
High Performance Interfacing and Switching
September 2005
Data Sheet
2005 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice.
Includes
High-
Performanc
e,
Low-Cost
“E-Series”
Features
■ High Performance Bus Switching
High bandwidth
– Up to 12.8 Gbps (SERDES)
– Up to 38 Gbps (without SERDES)
Up to 16 (15x10) FIFOs for data buffering
High speed performance
–fMAX = 360MHz
–tPD = 3.0ns
–tCO = 2.9ns
–tS = 2.0ns
Built-in programmable control logic capability
I/O intensive: 64 to 256 I/Os
Expanded MUX capability up to 188:1 MUX
■ sysCLOCK PLL
Frequency synthesis and skew management
Clock multiply and divide capability
Clock shifting up to +/-2.35ns in 335ps steps
Up to four PLLs
■ sysIO Interfacing
LVCMOS 1.8, 2.5, 3.3 and LVTTL support for
standard board interfaces
SSTL 2/3 Class I and II support
HSTL Class I, III and IV support
GTL+, PCI-X for bus interfaces
LVPECL, LVDS and Bus LVDS differential support
Hot socketing
Programmable drive strength
■ Two Options Available
High-performance sysHSI (standard part number)
Low-cost, no sysHSI (“E-Series”)
■ sysHSI Blocks Provide up to 16 High-speed
Channels
Serializer/de-serializer (SERDES) included
Clock Data Recovery (CDR) built in
800 Mbps per channel
LVDS differential support
10B/12B support
– Encoding / decoding
– Bit alignment
– Symbol alignment
8B/10B support
– Bit alignment
– Symbol alignment
Source Synchronous support
■ Flexible Programming and Testing
IEEE 1532 compliant In-System Programmabil-
ity (ISP)
Boundary scan test through IEEE 1149.1
interface
3.3V, 2.5V or 1.8V power supplies
5V tolerant I/O for LVCMOS 3.3 and LVTTL
interfaces
Table 1. ispGDX2 Family Selection Guide
ispGDX2-64/E
ispGDX2-128/E
ispGDX2-256/E
I/Os
64
128
256
GDX Blocks
4
8
16
tPD
3.0ns
3.2ns
3.5ns
tS
2.0ns
tCO
2.9ns
3.1ns
3.2ns
fMAX (Toggle)
360MHz
330MHz
300MHz
Max Bandwidth
SERDES
1, 2
3.2Gbps
6.4Gbps
12.8Gbps
Without SERDES
3
11Gbps
21Gbps
38Gbps
sysHSI Channels
2
48
16
LVDS/Bus LVDS (Pairs)
32
64
128
PLLs
2
4
Package
100-ball fpBGA
208-ball fpBGA
484-ball fpBGA
1. Max number of SERDES channels per device * 800Mbps
2. “E-Series” does not support sysHSI.
3. fMAX (Toggle) * maximum I/Os divided by 2.
SELECT
DEVICES
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