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參數(shù)資料
| 型號： | LVX573 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | Octal D-Type Latch with 3-State Outputs With 5 V−Tolerant Inputs |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 112K |
| 代理商： | LVX573 |
MC74LVX573
http://onsemi.com
2
Figure 2. Logic Diagram
O0
D0
O1
D1
O2
D2
O3
D3
O4
D4
O5
D5
O6
D6
O7
D7
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
nLE
Q
D
LE
OE
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
11
1
Table 1. PIN NAMES
Pins
Function
OE
LE
D0D7
O0O7
Output Enable Input
Latch Enable Input
Data Inputs
3State Latch Outputs
INPUTS
OUTPUTS
OE
LE
Dn
On
OPERATING MODE
L
L
H
H
H
L
H
L
Transparent (Latch
Disabled); Read Latch
L
L
L
L
h
l
H
L
Latched (Latch Enabled)
Read Latch
L
L
X
NC
Hold; Read Latch
H
L
X
Z
Hold; Disabled Outputs
H
H
H
H
H
L
Z
Z
Transparent (Latch
Disabled); Disabled Outputs
H
H
L
L
h
l
Z
Z
Latched (Latch Enabled);
Disabled Outputs
H = High Voltage Level; h = High Voltage Level One Setup Time
Prior to the Latch Enable HightoLow Transition; L = Low
Voltage Level; l = Low Voltage Level One Setup Time Prior to the
Latch Enable HightoLow Transition; NC = No Change, State
Prior to the Latch Enable HightoLow Transition; X = High or
Low Voltage Level or Transitions are Acceptable; Z = High
Impedance State; For I
CC
Reasons DO NOT FLOAT Inputs.
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
out
CC
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